From: Florent Kermarrec Date: Sat, 15 Feb 2020 18:04:47 +0000 (+0100) Subject: soc_core: add back identifier X-Git-Tag: 24jan2021_ls180~663 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6576470179c8083e42231434afd1970c1d174fee;p=litex.git soc_core: add back identifier --- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 43a03bff..247685bc 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -881,7 +881,7 @@ class LiteXSoC(SoC): self.check_if_exists(name) if with_build_time: identifier += " " + build_time() - setattr(self.submodules, name, Identifier(ident)) + setattr(self.submodules, name, Identifier(identifier)) self.csr.add(name + "_mem", use_loc_if_exists=True) # Add UART ------------------------------------------------------------------------------------- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 0d59924e..d58b9f0f 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -169,6 +169,10 @@ class SoCCore(LiteXSoC): if integrated_main_ram_size: self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size) + # Add Identifier + if ident != "": + self.add_identifier("identifier", identifier=ident, with_build_time=ident_version) + # Add UART if with_uart: self.add_uart(name=uart_name, baudrate=uart_baudrate)