From: R Veera Kumar <vklr@vkten.in>
Date: Tue, 23 Nov 2021 12:13:58 +0000 (+0530)
Subject: Add expected state to case_addis_nonzero_r0 in alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~710
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=657951e6517650f39781371f5ae1d6f6f6c9dcc5;p=openpower-isa.git

Add expected state to case_addis_nonzero_r0 in alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 3bde8e27..091ebef9 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -202,7 +202,13 @@ class ALUTestCase(TestAccumulatorBase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[0] = random.randint(0, (1 << 64)-1)
-            self.add_case(Program(lst, bigendian), initial_regs)
+            e = ExpectedState(pc=4)
+            e.intregs[0] = initial_regs[0]
+            if imm < 0:
+                e.intregs[3] = (imm + 2**48)<<16
+            else:
+                e.intregs[3] = imm << 16
+            self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_rand_imm(self):
         insns = ["addi", "addis", "subfic"]