From: Stephen Twigg <sdtwigg@eecs.berkeley.edu>
Date: Tue, 15 Oct 2013 07:21:00 +0000 (-0700)
Subject: Fix bug where xs2 was not being properly respected.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=658188c92b337c85a472f6de8067518a2e95de7d;p=riscv-isa-sim.git

Fix bug where xs2 was not being properly respected.
---

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index a4766d4..2354f9f 100644
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -15,7 +15,7 @@ union rocc_insn_union_t
     rocc_insn_union_t u; \
     u.i = insn; \
     reg_t xs1 = u.r.xs1 ? RS1 : -1; \
-    reg_t xs2 = u.r.xs1 ? RS2 : -1; \
+    reg_t xs2 = u.r.xs2 ? RS2 : -1; \
     reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
     if (u.r.xd) \
       WRITE_RD(xd); \