From: Andreas Hansson <andreas.hansson@arm.com>
Date: Thu, 27 Sep 2012 12:59:25 +0000 (-0400)
Subject: Configs: Fix memtest cache latency to match new parameters
X-Git-Tag: stable_2013_06_16~375
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6596059d058d783205f6570206c1088fad18817d;p=gem5.git

Configs: Fix memtest cache latency to match new parameters

This patch changes the memtest config to use the new response latency
of the cache model.
---

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index e337fe2b1..b29a612e9 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -110,7 +110,8 @@ if len(treespec) < 1:
 
 # define prototype L1 cache
 proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
-                     latency = '1ns', tgts_per_mshr = 8)
+                     hit_latency = '1ns', response_latency = '1ns',
+                     tgts_per_mshr = 8)
 
 if options.blocking:
      proto_l1.mshrs = 1