From: Marco Elver <marco.elver@ed.ac.uk>
Date: Sun, 7 Jun 2015 19:02:40 +0000 (-0500)
Subject: ruby: Fix MESI consistency bug
X-Git-Tag: stable_2015_09_03~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6599dd87c8332e4db3d898c9a28531ce2740c37f;p=gem5.git

ruby: Fix MESI consistency bug

Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load
reordering, as the LQ is never notified of the invalidate.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
---

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index b449c4f2b..4f9928bf1 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1341,6 +1341,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   // transitions from SM
   transition(SM, Inv, IM) {
+    forward_eviction_to_cpu;
     fi_sendInvAck;
     dg_invalidate_sc;
     l_popRequestQueue;