From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 17:47:14 +0000 (-0700)
Subject: Update abc_box_id numbering
X-Git-Tag: working-ls180~881^2^2~290
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=659c04a68d15b20a9421ea5d154b259265f39494;p=yosys.git

Update abc_box_id numbering
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index e95602ab2..9f6f9c47e 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index bb9258e78..633e2d484 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -54,20 +54,20 @@ RAM128X1D 6 0 17 2
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 6 1 5 1
+FDRE 7 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE D S \$pastQ
 # Outputs: Q
-FDSE 7 0 5 1
+FDSE 8 0 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 8 0 5 1
+FDCE 9 0 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 9 0 5 1
+FDPE 10 0 5 1
 - 109 -46 - 0