From: Staf Verhaegen <staf@fibraservi.eu>
Date: Fri, 8 May 2020 17:23:35 +0000 (+0200)
Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65a21c71b9524844076238c64944700c66ac816e;p=libre-riscv-dev.git

Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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+From: Staf Verhaegen <staf@fibraservi.eu>
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 08 May 2020 19:23:35 +0200
+In-Reply-To: <CAPweEDzdkhVJuJ3_UqZTbd7i7vXJ5iiu3qz+LUBsFRJrzCcEmQ@mail.gmail.com>
+References: <CAPweEDw862-S1=Au1YbsKNy0629pa56eShp+2o_Avd96Auz8mw@mail.gmail.com>
+ <9191058ea0912f2b508a6f73ea567e5f@f-cpu.org>
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+Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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+Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 17:55 [+0100]:
+> On Fri, May 8, 2020 at 4:27 PM <whygee@f-cpu.org> wrote:
+> > To me JTAG/TAP/debug port shine from its absence.
+>=20
+> yep good catch.  added.
+
+I already have (alpha version) nmigen JTAG code: https://gitlab.com/Chips4M=
+akers/c4m-jtagStaf. id=3D"-x-evo-selection-start-marker">
+
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