From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 6 May 2020 12:26:24 +0000 (+0100)
Subject: mention need for DualPortSplitter class
X-Git-Tag: div_pipeline~1376
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65a2218914d3f9a82d161c4cb946e5332d49b666;p=soc.git

mention need for DualPortSplitter class
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index e5ae956a..00e9a9f2 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -110,6 +110,22 @@ class PortInterface(RecordObject):
         self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf
         self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit
 
+# TODO:
+class DualPortSplitter(Elaboratable):
+    """DualPortSplitter
+
+    * one incoming PortInterface
+    * two *OUTGOING* PortInterfaces
+    * uses LDSTSplitter to do it
+
+    (actually, thinking about it LDSTSplitter could simply be
+     modified to conform to PortInterface: one in, two out)
+
+    once that is done each pair of ports may be wired directly
+    to the dual ports of L0CacheBuffer
+    """
+    pass
+
 
 class LDSTPort(Elaboratable):
     def __init__(self, idx, regwid=64, addrwid=48):