From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:54:39 +0000 (+0200)
Subject: Fixed memory corruption with new SigSpec API in proc_mux
X-Git-Tag: yosys-0.4~482
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65a939cb2767623b95adcd2ec5e783b828c1f9eb;p=yosys.git

Fixed memory corruption with new SigSpec API in proc_mux
---

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index cd459d949..50ba8fa1e 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -68,20 +68,16 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	for (auto comp : compare)
 	{
 		RTLIL::SigSpec sig = signal;
-		sig.expand();
-		comp.expand();
 
 		// get rid of don't-care bits
 		assert(sig.size() == comp.size());
 		for (int i = 0; i < comp.size(); i++)
-			if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) {
-				sig.remove(i, 1);
-				comp.remove(i--, 1);
+			if (comp[i] == RTLIL::State::Sa) {
+				sig.remove(i);
+				comp.remove(i--);
 			}
 		if (comp.size() == 0)
 			return RTLIL::SigSpec();
-		sig.optimize();
-		comp.optimize();
 
 		if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
 		{