From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 May 2020 16:48:20 +0000 (+0100)
Subject: add zero_a flag to CompALUOpSubset
X-Git-Tag: div_pipeline~989
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65aceac3fa2cdc1bc34120551c23a9dff681c02e;p=soc.git

add zero_a flag to CompALUOpSubset
---

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 41a40ebf..d8a9be14 100644
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -20,6 +20,7 @@ class CompALUOpSubset(Record):
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
                   ('invert_a', 1),
+                  ('zero_a', 1),
                   ('invert_out', 1),
                   ('input_carry', CryIn),
                   ('output_carry', 1),
@@ -40,6 +41,7 @@ class CompALUOpSubset(Record):
         #self.cr = Signal(32, reset_less = True
         #self.xerc = XerBits(
         self.lk.reset_less = True
+        self.zero_a.reset_less = True
         self.invert_a.reset_less = True
         self.invert_out.reset_less = True
         self.input_carry.reset_less = True