From: lkcl <lkcl@web>
Date: Fri, 25 Dec 2020 13:50:21 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~922
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65adc2e914d9cdf972bd39b594486a20cba32475;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 2aade0cd1..aa047b086 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -24,6 +24,8 @@ The fundamentals are:
 * Once the loop is completed *only then* is the Program Counter
   allowed to move to the next instruction.
 
+Hardware implementors are free and clear to implement this as literally a for-loop in hardware (and simulators), sitting in between instruction decode and issue.  Higher performance systems may deploy SIMD backends and multi-issue, although it is strongly recommended to add predication capability into all SIMD backend units.
+
 In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source and destination have been "tagged" as Vectors, is simply:
 
     for i = 0 to VL-1: