From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 10:37:20 +0000 (+0000)
Subject: fix bitwidth issues for rv32 in mulh* and sra
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65b82ba8a58fd21f366ae9e340e25488d2a0e316;p=riscv-isa-sim.git

fix bitwidth issues for rv32 in mulh* and sra
---

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index d7a95e9..7578ae6 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,5 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr(rv_mul(sext32(RS1), sext32(RS2)),
-                        sv_reg_t(32U))));
+  WRITE_RD(sext32(rv_mulh(sext32(RS1), sext32(RS2))));
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index 724e661..7521899 100644
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,5 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr((rv_mul(sext32(RS1), sv_reg_uint32(RS2))),
-                  sv_reg_t(32U))));
+  WRITE_RD(sext32((rv_mulhsu(sext32(RS1), sv_reg_uint32(RS2)))));
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index dee66b0..dcfc243 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -2,6 +2,4 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else
-  WRITE_RD(sext32(rv_sr(rv_mul(sv_reg_uint32(RS1),
-                          sv_reg_uint32(RS2)),
-                        sv_reg_t(32U))));
+  WRITE_RD(sext32(rv_mulhu(sv_reg_uint32(RS1), sv_reg_uint32(RS2))));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6467e34..d346116 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -436,6 +436,9 @@ bool sv_proc_t::rv_int_op_prepare(SLHSTYPE const & lhs, SRHSTYPE const & rhs, \
                                  uint8_t &bitwidth) \
 {                                                                   \
     bitwidth = _insn->src_bitwidth;                                        \
+    if (bitwidth == 0) { \
+        bitwidth = xlen; \
+    } \
     if (bitwidth == xlen) {                                                \
         return true;                                                       \
     }                                                                   \
@@ -568,6 +571,21 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
     return lhs * rhs;
 }
 
+sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
+sv_sreg_t sv_proc_t::rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
+sv_sreg_t sv_proc_t::rv_mulh(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
+{
+    return (lhs * rhs) >> 32;
+}
+
 sv_reg_t sv_proc_t::rv_and(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
     return lhs & rhs;
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 28659af..4056c5f 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -130,6 +130,9 @@ public:
     sv_reg_t rv_mul(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_sreg_t rv_mul(sv_sreg_t const & lhs, sv_reg_t const & rhs);
     sv_sreg_t rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs);
+    sv_reg_t rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs);
+    sv_sreg_t rv_mulh(sv_sreg_t const & lhs, sv_sreg_t const & rhs);
+    sv_sreg_t rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_and(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_or(sv_reg_t const & lhs, sv_reg_t const & rhs);
     sv_reg_t rv_xor(sv_reg_t const & lhs, sv_reg_t const & rhs);