From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 27 Sep 2020 14:58:06 +0000 (-0300)
Subject: Convert yet another few tests to be able to use latest cxxsim
X-Git-Tag: 24jan2021_ls180~300
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65cb51110335999843be2a6e729d656d8e8bbc74;p=soc.git

Convert yet another few tests to be able to use latest cxxsim
---

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index 1e5aa8fc..0a18c77b 100644
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import os
diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 3b4c562e..2ed244f0 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -17,11 +17,10 @@ from soc.experiment.compalu_multi import MultiCompUnit
 from soc.decoder.power_enums import MicrOp
 from nmigen import Module
 from nmigen.cli import rtlil
-cxxsim = False
-if cxxsim:
-    from nmigen.sim.cxxsim import Simulator, Settle
-else:
-    from nmigen.back.pysim import Simulator, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 def wrap(process):
diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index cb827907..2e4d7a89 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 82dac148..7e0df81e 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import ISACaller, special_sprs
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index f94fecea..82e05e98 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -14,19 +14,10 @@ from soc.decoder.isa.caller import ISACaller, special_sprs
 import unittest
 from nmigen.cli import rtlil
 from nmigen import Module, Signal
-from nmigen.back.pysim import Delay, Settle
-# NOTE: to use this (set to True), at present it is necessary to check
-# out the cxxsim nmigen branch
-cxxsim = False
-if cxxsim:
-    try:
-        from nmigen.sim.cxxsim import Simulator
-    except ImportError:
-        print("nope, sorry, have to use nmigen cxxsim branch for now")
-        cxxsim = False
-        from nmigen.back.pysim import Simulator
-else:
-    from nmigen.back.pysim import Simulator
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 def get_cu_inputs(dec2, sim):
@@ -314,12 +305,8 @@ class TestRunner(unittest.TestCase):
                     yield from self.execute(alu, instruction, pdecode2, test)
 
         sim.add_sync_process(process)
-        print(dir(sim))
-        if cxxsim:
+        with sim.write_vcd("shift_rot_simulator.vcd"):
             sim.run()
-        else:
-            with sim.write_vcd("shift_rot_simulator.vcd"):
-                sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):