From: whitequark Date: Sat, 12 Oct 2019 22:40:30 +0000 (+0000) Subject: hdl.ast: rename Slice.end back to Slice.stop. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65d2e7232ae5e5b32f116b15c38b81f0758886f3;p=nmigen.git hdl.ast: rename Slice.end back to Slice.stop. It used to be called .stop in oMigen, and it's also called .stop in Python range and slice objects, so keep that. --- diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 70c0a48..1ef8132 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -186,7 +186,7 @@ class _RHSValueCompiler(_ValueCompiler): shape = value.shape() arg = self(value.value) shift = value.start - mask = (1 << (value.end - value.start)) - 1 + mask = (1 << (value.stop - value.start)) - 1 return lambda state: normalize((arg(state) >> shift) & mask, shape) def on_Part(self, value): @@ -265,7 +265,7 @@ class _LHSValueCompiler(_ValueCompiler): lhs_r = self.rhs_compiler(value.value) lhs_l = self(value.value) shift = value.start - mask = (1 << (value.end - value.start)) - 1 + mask = (1 << (value.stop - value.start)) - 1 def eval(state, rhs): lhs_value = lhs_r(state) lhs_value &= ~(mask << shift) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 990e4bd..2dfed0e 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -354,16 +354,16 @@ class _ValueCompiler(xfrm.ValueVisitor): raise NotImplementedError # :nocov: def on_Slice(self, value): - if value.start == 0 and value.end == len(value.value): + if value.start == 0 and value.stop == len(value.value): return self(value.value) sigspec = self._prepare_value_for_Slice(value.value) - if value.start == value.end: + if value.start == value.stop: return "{}" - elif value.start + 1 == value.end: + elif value.start + 1 == value.stop: return "{} [{}]".format(sigspec, value.start) else: - return "{} [{}:{}]".format(sigspec, value.end - 1, value.start) + return "{} [{}:{}]".format(sigspec, value.stop - 1, value.start) def on_ArrayProxy(self, value): index = self.s.expand(value.index) diff --git a/nmigen/compat/fhdl/structure.py b/nmigen/compat/fhdl/structure.py index f218ee4..91aea7f 100644 --- a/nmigen/compat/fhdl/structure.py +++ b/nmigen/compat/fhdl/structure.py @@ -17,13 +17,6 @@ def wrap(v): return Value.cast(v) -@extend(_Slice) -@property -@deprecated("instead of `_Slice.stop`, use `Slice.end`") -def stop(self): - return self.end - - @extend(Cat) @property @deprecated("instead of `Cat.l`, use `Cat.parts`") diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index e0a78fd..5d616c1 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -620,31 +620,37 @@ def Mux(sel, val1, val0): @final class Slice(Value): - def __init__(self, value, start, end, *, src_loc_at=0): + def __init__(self, value, start, stop, *, src_loc_at=0): if not isinstance(start, int): raise TypeError("Slice start must be an integer, not {!r}".format(start)) - if not isinstance(end, int): - raise TypeError("Slice end must be an integer, not {!r}".format(end)) + if not isinstance(stop, int): + raise TypeError("Slice stop must be an integer, not {!r}".format(stop)) n = len(value) if start not in range(-(n+1), n+1): raise IndexError("Cannot start slice {} bits into {}-bit value".format(start, n)) if start < 0: start += n - if end not in range(-(n+1), n+1): - raise IndexError("Cannot end slice {} bits into {}-bit value".format(end, n)) - if end < 0: - end += n - if start > end: - raise IndexError("Slice start {} must be less than slice end {}".format(start, end)) + if stop not in range(-(n+1), n+1): + raise IndexError("Cannot stop slice {} bits into {}-bit value".format(stop, n)) + if stop < 0: + stop += n + if start > stop: + raise IndexError("Slice start {} must be less than slice stop {}".format(start, stop)) super().__init__(src_loc_at=src_loc_at) self.value = Value.cast(value) self.start = start - self.end = end + self.stop = stop + + # TODO(nmigen-0.2): remove this + @property + @deprecated("instead of `slice.end`, use `slice.stop`") + def end(self): + return self.stop def shape(self): - return Shape(self.end - self.start) + return Shape(self.stop - self.start) def _lhs_signals(self): return self.value._lhs_signals() @@ -653,7 +659,7 @@ class Slice(Value): return self.value._rhs_signals() def __repr__(self): - return "(slice {} {}:{})".format(repr(self.value), self.start, self.end) + return "(slice {} {}:{})".format(repr(self.value), self.start, self.stop) @final diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py index 768db51..889e4b0 100644 --- a/nmigen/hdl/xfrm.py +++ b/nmigen/hdl/xfrm.py @@ -160,7 +160,7 @@ class ValueTransformer(ValueVisitor): return Operator(value.operator, [self.on_value(o) for o in value.operands]) def on_Slice(self, value): - return Slice(self.on_value(value.value), value.start, value.end) + return Slice(self.on_value(value.value), value.start, value.stop) def on_Part(self, value): return Part(self.on_value(value.value), self.on_value(value.offset), diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py index e403a5b..b7e9647 100644 --- a/nmigen/test/test_hdl_ast.py +++ b/nmigen/test/test_hdl_ast.py @@ -166,11 +166,11 @@ class ValueTestCase(FHDLTestCase): s1 = Const(10)[0] self.assertIsInstance(s1, Slice) self.assertEqual(s1.start, 0) - self.assertEqual(s1.end, 1) + self.assertEqual(s1.stop, 1) s2 = Const(10)[-1] self.assertIsInstance(s2, Slice) self.assertEqual(s2.start, 3) - self.assertEqual(s2.end, 4) + self.assertEqual(s2.stop, 4) with self.assertRaises(IndexError, msg="Cannot index 5 bits into 4-bit value"): Const(10)[5] @@ -179,22 +179,22 @@ class ValueTestCase(FHDLTestCase): s1 = Const(10)[1:3] self.assertIsInstance(s1, Slice) self.assertEqual(s1.start, 1) - self.assertEqual(s1.end, 3) + self.assertEqual(s1.stop, 3) s2 = Const(10)[1:-2] self.assertIsInstance(s2, Slice) self.assertEqual(s2.start, 1) - self.assertEqual(s2.end, 2) + self.assertEqual(s2.stop, 2) s3 = Const(31)[::2] self.assertIsInstance(s3, Cat) self.assertIsInstance(s3.parts[0], Slice) self.assertEqual(s3.parts[0].start, 0) - self.assertEqual(s3.parts[0].end, 1) + self.assertEqual(s3.parts[0].stop, 1) self.assertIsInstance(s3.parts[1], Slice) self.assertEqual(s3.parts[1].start, 2) - self.assertEqual(s3.parts[1].end, 3) + self.assertEqual(s3.parts[1].stop, 3) self.assertIsInstance(s3.parts[2], Slice) self.assertEqual(s3.parts[2].start, 4) - self.assertEqual(s3.parts[2].end, 5) + self.assertEqual(s3.parts[2].stop, 5) def test_getitem_wrong(self): with self.assertRaises(TypeError, @@ -497,16 +497,16 @@ class SliceTestCase(FHDLTestCase): def test_start_end_negative(self): c = Const(0, 8) s1 = Slice(c, 0, -1) - self.assertEqual((s1.start, s1.end), (0, 7)) + self.assertEqual((s1.start, s1.stop), (0, 7)) s1 = Slice(c, -4, -1) - self.assertEqual((s1.start, s1.end), (4, 7)) + self.assertEqual((s1.start, s1.stop), (4, 7)) def test_start_end_wrong(self): with self.assertRaises(TypeError, msg="Slice start must be an integer, not 'x'"): Slice(0, "x", 1) with self.assertRaises(TypeError, - msg="Slice end must be an integer, not 'x'"): + msg="Slice stop must be an integer, not 'x'"): Slice(0, 1, "x") def test_start_end_out_of_range(self): @@ -515,10 +515,10 @@ class SliceTestCase(FHDLTestCase): msg="Cannot start slice 10 bits into 8-bit value"): Slice(c, 10, 12) with self.assertRaises(IndexError, - msg="Cannot end slice 12 bits into 8-bit value"): + msg="Cannot stop slice 12 bits into 8-bit value"): Slice(c, 0, 12) with self.assertRaises(IndexError, - msg="Slice start 4 must be less than slice end 2"): + msg="Slice start 4 must be less than slice stop 2"): Slice(c, 4, 2) def test_repr(self):