From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 21:29:00 +0000 (-0700)
Subject: Add DSP_SIGNEDONLY back
X-Git-Tag: working-ls180~1039^2~278
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65de9aaaa9d744686e235ff8701cd997cd2dc891;p=yosys.git

Add DSP_SIGNEDONLY back
---

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 5ff0e03aa..6cd5128a6 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -55,6 +55,22 @@ module \$mul (A, B, Y);
 	if (A_SIGNED != B_SIGNED)
 		wire _TECHMAP_FAIL_ = 1;
 	// NB: A_SIGNED == B_SIGNED from here
+`ifdef DSP_SIGNEDONLY
+	else if (!A_SIGNED) begin
+		wire [1:0] _;
+		\$mul #(
+			.A_SIGNED(1),
+			.B_SIGNED(1),
+			.A_WIDTH(A_WIDTH + 1),
+			.B_WIDTH(B_WIDTH + 1),
+			.Y_WIDTH(Y_WIDTH + 2)
+		) _TECHMAP_REPLACE_ (
+			.A({1'b0, A}),
+			.B({1'b0, B}),
+			.Y({_, Y})
+		);
+	end
+`endif
 	else if (A_WIDTH < B_WIDTH)
 		\$mul #(
 			.A_SIGNED(B_SIGNED),