From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 May 2021 13:11:18 +0000 (+0100)
Subject: add new fp load / store with update unit test
X-Git-Tag: 0.0.3~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65df92528001d16923c4539693d39f2a723b4f1c;p=openpower-isa.git

add new fp load / store with update unit test
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index b93d51be..c2bcec4c 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -207,15 +207,22 @@ def SINGLE(FRS):
     # result - WORD - start off all zeros
     WORD = SelectableInt(0, 32)
 
+    e = FRS[1:12]
+    m = FRS[9:32]
+    s = FRS[0]
+
+    print ("SINGLE", FRS)
+    print ("s e m", s.value, e.value, m.value)
+
     #No Denormalization Required (includes Zero / Infinity / NaN)
-    if FRS[1:12].value > 896 or FRS[1:64].value  == 0:
+    if e.value > 896 or FRS[1:64].value  == 0:
           WORD[0:2] = FRS[0:2]
           WORD[2:32] = FRS[5:35]
 
     #Denormalization Required
-    if FRS[1:12].value  >= 874 and FRS[1:12].value  <= 896:
+    if e.value  >= 874 and e.value  <= 896:
           sign = FRS[0]
-          exp = FRS[1:12] - 1023
+          exp = e - 1023
           frac = selectconcat(SelectableInt(1, 1), FRS[12:64])
           # denormalize operand
           while exp.value  < -126:
@@ -226,6 +233,8 @@ def SINGLE(FRS):
           WORD[9:32] = frac[1:24]
     #else WORD = undefined # return zeros
 
+    print ("WORD", WORD)
+
     return WORD
 
 # XXX NOTE: these are very quick hacked functions for utterly basic
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index b8e4f1d3..61af16c6 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -365,6 +365,8 @@ def get_pdecode_idx_in(dec2, name):
                                      in2, in2_isvec)
     print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
                                      in3, in3_isvec)
+    print ("get_pdecode_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
+                                     in3, in3_isvec)
     # identify which regnames map to in1/2/3
     if name == 'RA':
         if (in1_sel == In1Sel.RA.value or
@@ -399,8 +401,8 @@ def get_pdecode_idx_in(dec2, name):
     elif name == 'FRS':
         if in1_sel == In1Sel.FRS.value:
             return in1, in1_isvec
-        if in2_sel == In2Sel.FRS.value:
-            return in2, in2_isvec
+        if in3_sel == In3Sel.FRS.value:
+            return in3, in3_isvec
     return None, False
 
 
@@ -423,7 +425,7 @@ def get_pdecode_cr_out(dec2, name):
     if name == 'CR0':
         if out_sel == CROutSel.CR0.value:
             return out, o_isvec
-    print ("get_pdecode_idx_out not found", name)
+    print ("get_pdecode_cr_out not found", name)
     return None, False
 
 
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 05b7ebd2..79da6467 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -38,6 +38,30 @@ class DecoderTestCase(FHDLTestCase):
             print("FPR 1", sim.fpr(1))
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 
+    def test_fp_single_ldst(self):
+        """>>> lst = ["lfsx 1, 1, 0",   # load fp 1 from mem location 0
+                      "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
+                      "lfsu 2, 0(1)",   # re-load from UPDATED r1
+                     ]
+        """
+        lst = ["lfsx 1, 1, 0",
+               "stfsu 1, 16(1)",
+               "lfs 2, 0(1)",
+                     ]
+        initial_mem = {0x0000: (0x42013333, 8),
+                       0x0008: (0x42026666, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_mem=initial_mem)
+            print("FPR 1", sim.fpr(1))
+            print("FPR 2", sim.fpr(2))
+            print("GPR 1", sim.gpr(1)) # should be 0x10 due to update
+            self.assertEqual(sim.gpr(1), SelectableInt(0x10, 64))
+            self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None):
         if initial_regs is None: