From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 18:02:14 +0000 (-0700)
Subject: Format macc.v
X-Git-Tag: working-ls180~1039^2~96
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65fa8adf6c834cc3c73300a19d4fe96c31b8d361;p=yosys.git

Format macc.v
---

diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
index 6c3676c83..757c36a66 100644
--- a/tests/ice40/macc.v
+++ b/tests/ice40/macc.v
@@ -13,13 +13,13 @@ reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
 assign c = reg_tmp_c;
 always @(posedge clk)
 begin
-if(set)
-begin
-reg_tmp_c <= 0;
-end
-else
-begin
-reg_tmp_c <= a * b + c;
-end
+    if(set)
+    begin
+        reg_tmp_c <= 0;
+    end
+    else
+    begin
+        reg_tmp_c <= a * b + c;
+    end
 end
 endmodule