From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 12:37:17 +0000 (+0100)
Subject: add CA/CA32 to list of special regs
X-Git-Tag: div_pipeline~504
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=660527d66dbf97f48375251dd876c489f3969dc7;p=soc.git

add CA/CA32 to list of special regs
---

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index d2466eac..55db59cd 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -611,7 +611,7 @@ class PowerParser:
         name = p[1]
         if name in self.available_op_fields:
             self.op_fields.add(name)
-        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR']:
+        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR', 'CA', 'CA32']:
             self.special_regs.add(name)
             self.write_regs.add(name) # and add to list to write
         p[0] = ast.Name(id=name, ctx=ast.Load())