From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 16 Dec 2022 07:16:55 +0000 (-0800)
Subject: register_allocator works!
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6605a9fdec2903884e0ffee6be6c420f21fa3301;p=bigint-presentation-code.git

register_allocator works!
---

diff --git a/src/bigint_presentation_code/_tests/test_toom_cook.py b/src/bigint_presentation_code/_tests/test_toom_cook.py
index 0b1f477..ae8b6c0 100644
--- a/src/bigint_presentation_code/_tests/test_toom_cook.py
+++ b/src/bigint_presentation_code/_tests/test_toom_cook.py
@@ -489,8 +489,17 @@ class TestToomCook(unittest.TestCase):
         fn = code.fn
         assigned_registers = allocate_registers(
             fn, debug_out=sys.stdout, dump_graph=GraphDumper(self))
+        print(repr(assigned_registers))
         self.assertEqual(
             repr(assigned_registers), "{"
+            "<mul_1_cast_pp_zero.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
+            "<mul_1_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_1_pp_concat.out0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
+            "<mul_1_cast_pp_zero.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
             "<mul_1_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
             "<mul_1_pp_concat.inp0.copy.outputs[0]: <I64>>: "
@@ -503,12 +512,6 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
             "<mul_1_pp_concat.inp4.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
-            "<mul_1_cast_pp_zero.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
-            "<mul_1_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
-            "<mul_1_pp_concat.out0.copy.outputs[0]: <I64*5>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
             "<mul_1_add.inp1.copy.outputs[0]: <I64*5>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
             "<mul_1_mul.outputs[0]: <I64*3>>: "
@@ -527,32 +530,14 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
             "<mul_1_pp_concat.outputs[0]: <I64*5>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=5), "
-            "<mul_zero.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_0_mul.inp2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_0_mul.outputs[1]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_1_mul.inp2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_1_mul.outputs[1]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_1_mul.out1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_2_mul.inp2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_2_mul.outputs[1]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_2_mul.out1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_2_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
-            "<mul_2_pp_concat.out0.copy.outputs[0]: <I64*4>>: "
-            "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
             "<mul_2_mul_rt_spread.out1.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
             "<mul_2_pp_concat.outputs[0]: <I64*4>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
+            "<mul_2_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
+            "<mul_2_pp_concat.out0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
             "<mul_2_add.inp1.copy.outputs[0]: <I64*4>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=4), "
             "<mul_2_mul.outputs[0]: <I64*3>>: "
@@ -577,10 +562,24 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
             "<mul_2_pp_concat.inp3.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
-            "<mul_1_cast_pp_zero.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
-            "<mul_1_cast_retval_zero.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_zero.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_0_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_0_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_1_mul.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.outputs[1]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
+            "<mul_2_mul.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
             "<mul_0_mul_rt_spread.inp0.copy.outputs[0]: <I64*3>>: "
             "Loc(kind=LocKind.GPR, start=14, reg_len=3), "
             "<mul_0_mul_rt_spread.outputs[0]: <I64>>: "
@@ -599,12 +598,12 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
             "<mul_1_add.inp0.copy.outputs[0]: <I64*5>>: "
             "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_0_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
             "<mul_0_mul.out1.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
             "<mul_1_retval_concat.out0.copy.outputs[0]: <I64*5>>: "
             "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
-            "<mul_0_mul_rt_spread.out2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
             "<mul_1_cast_retval_zero.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
             "<mul_1_retval_concat.inp0.copy.outputs[0]: <I64>>: "
@@ -617,6 +616,34 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
             "<mul_1_retval_concat.inp4.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_2_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
+            "<mul_1_sum_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_0_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
+            "<mul_concat.out0.copy.outputs[0]: <I64*6>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
+            "<mul_2_add.inp0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_1_add.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_1_add.out0.copy.outputs[0]: <I64*5>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
+            "<mul_2_sum_spread.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_concat.inp0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
+            "<mul_concat.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
+            "<mul_concat.inp2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
+            "<mul_concat.inp3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
+            "<mul_concat.inp4.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_concat.inp5.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
             "<mul_1_sum_spread.inp0.copy.outputs[0]: <I64*5>>: "
             "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
             "<mul_1_sum_spread.outputs[0]: <I64>>: "
@@ -633,13 +660,11 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
             "<mul_2_retval_concat.outputs[0]: <I64*4>>: "
             "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
-            "<mul_0_mul_rt_spread.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
-            "<mul_concat.out0.copy.outputs[0]: <I64*6>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
-            "<mul_1_sum_spread.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
-            "<mul_2_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "<mul_1_sum_spread.out3.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
+            "<mul_2_retval_concat.out0.copy.outputs[0]: <I64*4>>: "
+            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
+            "<mul_1_sum_spread.out4.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
             "<mul_1_sum_spread.out1.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
@@ -651,32 +676,6 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
             "<mul_2_retval_concat.inp3.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
-            "<mul_1_sum_spread.out4.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
-            "<mul_1_sum_spread.out3.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
-            "<mul_2_retval_concat.out0.copy.outputs[0]: <I64*4>>: "
-            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
-            "<mul_2_add.inp0.copy.outputs[0]: <I64*4>>: "
-            "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
-            "<mul_1_add.outputs[0]: <I64*5>>: "
-            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
-            "<mul_1_add.out0.copy.outputs[0]: <I64*5>>: "
-            "Loc(kind=LocKind.GPR, start=15, reg_len=5), "
-            "<mul_2_sum_spread.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
-            "<mul_concat.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
-            "<mul_concat.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
-            "<mul_concat.inp2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
-            "<mul_concat.inp3.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
-            "<mul_concat.inp4.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
-            "<mul_concat.inp5.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
             "<mul_2_add.outputs[0]: <I64*4>>: "
             "Loc(kind=LocKind.GPR, start=16, reg_len=4), "
             "<mul_2_add.out0.copy.outputs[0]: <I64*4>>: "
@@ -699,52 +698,54 @@ class TestToomCook(unittest.TestCase):
             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
             "<store_dest.inp0.copy.outputs[0]: <I64*6>>: "
             "Loc(kind=LocKind.GPR, start=14, reg_len=6), "
-            "<mul_zero.out0.copy.outputs[0]: <I64>>: "
+            "<mul_1_cast_retval_zero.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=8, reg_len=1), "
-            "<ptr_in.out0.copy.outputs[0]: <I64>>: "
+            "<mul_zero.out0.copy.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "<ptr_in.out0.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
             "<store_dest.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
             "<load_lhs.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
             "<load_rhs.inp0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
             "<ptr_in.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
-            "<mul_rhs_spread.out2.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
             "<mul_2_mul.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
             "<load_rhs.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
             "<load_rhs.out0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "<mul_rhs_spread.out2.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
+            "<mul_rhs_spread.out1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
+            "<mul_1_mul.inp1.copy.outputs[0]: <I64>>: "
+            "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
             "<mul_rhs_spread.inp0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
             "<mul_rhs_spread.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
             "<mul_rhs_spread.outputs[1]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
             "<mul_rhs_spread.outputs[2]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
             "<mul_rhs_spread.out0.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
             "<mul_0_mul.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
-            "<mul_rhs_spread.out1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
-            "<mul_1_mul.inp1.copy.outputs[0]: <I64>>: "
-            "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
+            "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
             "<load_lhs.out0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<load_lhs.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<mul_0_mul.inp0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<mul_1_mul.inp0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<mul_2_mul.inp0.copy.outputs[0]: <I64*3>>: "
-            "Loc(kind=LocKind.GPR, start=20, reg_len=3), "
+            "Loc(kind=LocKind.GPR, start=24, reg_len=3), "
             "<mul_zero2.outputs[0]: <I64>>: "
             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
             "<mul_zero2.out0.copy.outputs[0]: <I64>>: "
@@ -872,39 +873,41 @@ class TestToomCook(unittest.TestCase):
             fn, debug_out=sys.stdout, dump_graph=GraphDumper(self))
         gen_asm_state = GenAsmState(assigned_registers)
         fn.gen_asm(gen_asm_state)
+        print(gen_asm_state.output)
         self.assertEqual(gen_asm_state.output, [
-            'or 9, 3, 3',
+            'or 10, 3, 3',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.ld *20, 48(9)',
+            'sv.ld *24, 48(10)',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.ld *10, 72(9)',
+            'sv.ld *20, 72(10)',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'addi 6, 0, 0',
-            'or 8, 6, 6',
+            'or 9, 6, 6',
             'setvl 0, 0, 3, 0, 1, 1',
             'addi 3, 0, 0',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 6, 8, 8',
+            'or 6, 9, 9',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.maddedu *14, *20, 10, 6',
+            'sv.maddedu *14, *24, 20, 6',
             'setvl 0, 0, 3, 0, 1, 1',
             'or 17, 6, 6',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 6, 8, 8',
+            'or 6, 9, 9',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.maddedu *3, *20, 11, 6',
+            'sv.maddedu *3, *24, 21, 6',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'addi 18, 0, 0',
+            'addi 8, 0, 0',
+            'or 18, 8, 8',
             'addi 7, 0, 0',
             'setvl 0, 0, 5, 0, 1, 1',
             'or 19, 18, 18',
@@ -921,9 +924,9 @@ class TestToomCook(unittest.TestCase):
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 6, 8, 8',
+            'or 6, 9, 9',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.maddedu *3, *20, 12, 6',
+            'sv.maddedu *3, *24, 22, 6',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
@@ -946,7 +949,7 @@ class TestToomCook(unittest.TestCase):
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.std *14, 0(9)',
+            'sv.std *14, 0(10)'
         ])
 
     def toom_2_mul_256x256(self, lhs_signed, rhs_signed):
@@ -1084,603 +1087,371 @@ class TestToomCook(unittest.TestCase):
             fn, debug_out=sys.stdout, dump_graph=GraphDumper(self))
         gen_asm_state = GenAsmState(assigned_registers)
         fn.gen_asm(gen_asm_state)
+        print(gen_asm_state.output)
         self.assertEqual(gen_asm_state.output, [
-            'or 45, 3, 3',
+            'or 49, 3, 3',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 7, 45, 45',
+            'or 3, 49, 49',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.ld *3, 64(7)',
+            'sv.ld *39, 64(3)',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *8, *3, *3',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 7, 45, 45',
+            'or 3, 49, 49',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.ld *3, 96(7)',
+            'sv.ld *14, 96(3)',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *18, *3, *3',
+            'sv.or *3, *14, *14',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *3, *8, *8',
+            'sv.or *14, *39, *39',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *9, *3, *3',
-            'or 3, 9, 9',
-            'or 8, 10, 10',
-            'or 6, 11, 11',
-            'or 7, 12, 12',
+            'or 32, 16, 16',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 4, 8, 8',
-            'or 5, 6, 6',
+            'or 16, 32, 32',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or/mrr *4, *3, *3',
+            'sv.or *30, *14, *14',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 3, 7, 7',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 46, 3, 3',
+            'or 48, 17, 17',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or *3, *4, *4',
+            'sv.or *14, *30, *30',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or/mrr *5, *3, *3',
-            'or 4, 5, 5',
-            'or 9, 6, 6',
-            'or 8, 7, 7',
-            'addi 3, 0, 0',
-            'or 7, 3, 3',
+            'or 41, 16, 16',
+            'addi 7, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 9, 9',
-            'or 5, 8, 8',
-            'or 6, 7, 7',
+            'or 16, 41, 41',
+            'or 17, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *35, *3, *3',
+            'sv.or *30, *14, *14',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 3, 46, 46',
+            'or 17, 48, 48',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 4, 3, 3',
-            'addi 3, 0, 0',
-            'or 7, 3, 3',
+            'sv.or *7, *17, *17',
+            'addi 8, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 7, 7',
-            'or 5, 7, 7',
-            'or 6, 7, 7',
+            'or 9, 8, 8',
+            'or 10, 8, 8',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
+            'sv.or *17, *7, *7',
             'setvl 0, 0, 4, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *35, *35',
+            'sv.or *39, *30, *30',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *7, *3, *3',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.adde *3, *14, *7',
+            'sv.adde *34, *39, *17',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *40, *3, *3',
+            'sv.or *44, *34, *34',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *3, *18, *18',
+            'sv.or *14, *3, *3',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *9, *3, *3',
-            'or 3, 9, 9',
-            'or 8, 10, 10',
-            'or 6, 11, 11',
-            'or 7, 12, 12',
+            'or 3, 14, 14',
+            'or 10, 17, 17',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 4, 8, 8',
-            'or 5, 6, 6',
+            'or 14, 3, 3',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or/mrr *4, *3, *3',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 3, 7, 7',
             'setvl 0, 0, 3, 0, 1, 1',
-            'or 47, 3, 3',
+            'sv.or *17, *10, *10',
+            'or 43, 17, 17',
             'setvl 0, 0, 3, 0, 1, 1',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or *3, *4, *4',
+            'sv.or *7, *14, *14',
             'setvl 0, 0, 3, 0, 1, 1',
-            'sv.or/mrr *5, *3, *3',
-            'or 4, 5, 5',
-            'or 9, 6, 6',
-            'or 8, 7, 7',
-            'addi 3, 0, 0',
-            'or 7, 3, 3',
+            'or 3, 7, 7',
+            'or 4, 8, 8',
+            'or 5, 9, 9',
+            'addi 7, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 9, 9',
-            'or 5, 8, 8',
             'or 6, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *18, *3, *3',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 3, 47, 47',
+            'or 17, 43, 43',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 4, 3, 3',
-            'addi 3, 0, 0',
-            'or 7, 3, 3',
+            'addi 7, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 7, 7',
-            'or 5, 7, 7',
-            'or 6, 7, 7',
+            'or 18, 7, 7',
+            'or 19, 7, 7',
+            'or 20, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *18, *18',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *7, *3, *3',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.adde *3, *14, *7',
+            'sv.adde *7, *3, *17',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *29, *3, *3',
+            'sv.or *38, *7, *7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *3, *18, *18',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or/mrr *5, *3, *3',
-            'or 4, 5, 5',
-            'or 9, 6, 6',
-            'or 34, 7, 7',
-            'or 33, 8, 8',
-            'addi 3, 0, 0',
-            'or 28, 3, 3',
+            'addi 7, 0, 0',
+            'or 35, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
-            'addi 3, 0, 0',
+            'addi 7, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *35, *35',
-            'or 8, 4, 4',
-            'or 7, 28, 28',
+            'sv.or *14, *30, *30',
+            'or 7, 3, 3',
+            'or 21, 35, 35',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *22, *14, 7, 21',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 24, 7, 7',
+            'or 26, 21, 21',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 27, 3, 3',
-            'or 23, 4, 4',
-            'or 19, 5, 5',
-            'or 18, 6, 6',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *35, *35',
-            'or 8, 9, 9',
-            'or 7, 28, 28',
+            'sv.or *14, *30, *30',
+            'or 34, 4, 4',
+            'or 21, 35, 35',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *7, *14, 34, 21',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 22, 7, 7',
+            'or 11, 21, 21',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 21, 3, 3',
-            'or 20, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'addi 3, 0, 0',
-            'or 10, 3, 3',
-            'addi 3, 0, 0',
-            'or 9, 3, 3',
+            'addi 14, 0, 0',
+            'or 27, 14, 14',
+            'addi 14, 0, 0',
+            'or 12, 14, 14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 3, 23, 23',
-            'or 4, 19, 19',
-            'or 5, 18, 18',
-            'or 6, 24, 24',
-            'or 7, 10, 10',
-            'or 8, 10, 10',
+            'or 28, 27, 27',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
-            'or 3, 21, 21',
-            'or 4, 20, 20',
-            'or 5, 12, 12',
-            'or 6, 11, 11',
-            'or 7, 22, 22',
-            'or 8, 9, 9',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *20, *14, *14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.adde *3, *20, *14',
+            'sv.adde *23, *23, *7',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 26, 3, 3',
-            'or 25, 4, 4',
-            'or 24, 5, 5',
-            'or 23, 6, 6',
-            'or 19, 7, 7',
-            'or 18, 8, 8',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *35, *35',
-            'or 8, 34, 34',
-            'or 7, 28, 28',
+            'sv.or *14, *30, *30',
+            'or 34, 5, 5',
+            'or 21, 35, 35',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *7, *14, 34, 21',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 22, 7, 7',
+            'or 11, 21, 21',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 21, 3, 3',
-            'or 20, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'addi 3, 0, 0',
-            'or 10, 3, 3',
-            'addi 3, 0, 0',
-            'or 9, 3, 3',
+            'addi 14, 0, 0',
+            'or 29, 14, 14',
+            'addi 14, 0, 0',
+            'or 12, 14, 14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 3, 25, 25',
-            'or 4, 24, 24',
-            'or 5, 23, 23',
-            'or 6, 19, 19',
-            'or 7, 18, 18',
-            'or 8, 10, 10',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
-            'or 3, 21, 21',
-            'or 4, 20, 20',
-            'or 5, 12, 12',
-            'or 6, 11, 11',
-            'or 7, 22, 22',
-            'or 8, 9, 9',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *20, *14, *14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.adde *3, *20, *14',
+            'sv.adde *24, *24, *7',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 20, 3, 3',
-            'or 19, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'or 10, 7, 7',
-            'or 9, 8, 8',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *35, *35',
-            'or 8, 33, 33',
-            'or 7, 28, 28',
+            'sv.or *14, *30, *30',
+            'or 8, 6, 6',
+            'or 21, 35, 35',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *3, *14, 8, 21',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 18, 7, 7',
+            'or 7, 21, 21',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 17, 3, 3',
-            'or 16, 4, 4',
-            'or 15, 5, 5',
-            'or 14, 6, 6',
             'setvl 0, 0, 5, 0, 1, 1',
-            'or 3, 19, 19',
-            'or 4, 12, 12',
-            'or 5, 11, 11',
-            'or 6, 10, 10',
-            'or 7, 9, 9',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
-            'or 3, 17, 17',
-            'or 4, 16, 16',
-            'or 5, 15, 15',
-            'or 6, 14, 14',
-            'or 7, 18, 18',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *14, *8, *8',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.adde *3, *14, *8',
+            'sv.adde *25, *25, *3',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'or 16, 3, 3',
-            'or 15, 4, 4',
-            'or 14, 5, 5',
-            'or 12, 6, 6',
-            'or 11, 7, 7',
             'setvl 0, 0, 8, 0, 1, 1',
-            'or 3, 27, 27',
-            'or 4, 26, 26',
-            'or 5, 20, 20',
-            'or 6, 16, 16',
-            'or 7, 15, 15',
-            'or 8, 14, 14',
-            'or 9, 12, 12',
-            'or 10, 11, 11',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *21, *3, *3',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *3, *29, *29',
+            'sv.or *7, *38, *38',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or/mrr *5, *3, *3',
-            'or 4, 5, 5',
-            'or 9, 6, 6',
-            'or 39, 7, 7',
-            'or 38, 8, 8',
+            'or 38, 7, 7',
+            'or 39, 8, 8',
+            'or 40, 9, 9',
+            'or 41, 10, 10',
             'addi 3, 0, 0',
-            'or 37, 3, 3',
+            'or 10, 3, 3',
             'setvl 0, 0, 4, 0, 1, 1',
             'addi 3, 0, 0',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *40, *40',
-            'or 8, 4, 4',
-            'or 7, 37, 37',
+            'sv.or *34, *44, *44',
+            'or 9, 38, 38',
+            'or 7, 10, 10',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *14, *34, 9, 7',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 32, 7, 7',
+            'or 18, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 36, 3, 3',
-            'or 31, 4, 4',
-            'or 19, 5, 5',
-            'or 18, 6, 6',
+            'or 30, 14, 14',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *40, *40',
-            'or 8, 9, 9',
-            'or 7, 37, 37',
+            'or 9, 39, 39',
+            'or 7, 10, 10',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *3, *44, 9, 7',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 30, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 29, 3, 3',
-            'or 20, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'addi 3, 0, 0',
-            'or 10, 3, 3',
-            'addi 3, 0, 0',
-            'or 9, 3, 3',
+            'addi 9, 0, 0',
+            'or 19, 9, 9',
+            'addi 9, 0, 0',
+            'or 8, 9, 9',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 3, 31, 31',
-            'or 4, 19, 19',
-            'or 5, 18, 18',
-            'or 6, 32, 32',
-            'or 7, 10, 10',
-            'or 8, 10, 10',
+            'or 20, 19, 19',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
-            'or 3, 29, 29',
-            'or 4, 20, 20',
-            'or 5, 12, 12',
-            'or 6, 11, 11',
-            'or 7, 30, 30',
-            'or 8, 9, 9',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *29, *14, *14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.adde *3, *29, *14',
+            'sv.adde *15, *15, *3',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 35, 3, 3',
-            'or 33, 4, 4',
-            'or 32, 5, 5',
-            'or 31, 6, 6',
-            'or 19, 7, 7',
-            'or 18, 8, 8',
+            'or 31, 15, 15',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *40, *40',
-            'or 8, 39, 39',
-            'or 7, 37, 37',
+            'or 9, 40, 40',
+            'or 7, 10, 10',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *3, *44, 9, 7',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 30, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 29, 3, 3',
-            'or 20, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'addi 3, 0, 0',
-            'or 10, 3, 3',
-            'addi 3, 0, 0',
-            'or 9, 3, 3',
+            'addi 9, 0, 0',
+            'or 21, 9, 9',
+            'addi 8, 0, 0',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 3, 33, 33',
-            'or 4, 32, 32',
-            'or 5, 31, 31',
-            'or 6, 19, 19',
-            'or 7, 18, 18',
-            'or 8, 10, 10',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
-            'or 3, 29, 29',
-            'or 4, 20, 20',
-            'or 5, 12, 12',
-            'or 6, 11, 11',
-            'or 7, 30, 30',
-            'or 8, 9, 9',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *29, *14, *14',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 6, 0, 1, 1',
-            'sv.adde *3, *29, *14',
+            'sv.adde *16, *16, *3',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
             'setvl 0, 0, 6, 0, 1, 1',
-            'or 20, 3, 3',
-            'or 19, 4, 4',
-            'or 12, 5, 5',
-            'or 11, 6, 6',
-            'or 10, 7, 7',
-            'or 9, 8, 8',
+            'or 32, 16, 16',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.or *14, *40, *40',
-            'or 8, 38, 38',
-            'or 7, 37, 37',
+            'or 9, 41, 41',
+            'or 7, 10, 10',
             'setvl 0, 0, 4, 0, 1, 1',
-            'sv.maddedu *3, *14, 8, 7',
+            'sv.maddedu *38, *44, 9, 7',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 18, 7, 7',
+            'or 42, 7, 7',
             'setvl 0, 0, 4, 0, 1, 1',
             'setvl 0, 0, 4, 0, 1, 1',
-            'or 17, 3, 3',
-            'or 16, 4, 4',
-            'or 15, 5, 5',
-            'or 14, 6, 6',
             'setvl 0, 0, 5, 0, 1, 1',
-            'or 3, 19, 19',
-            'or 4, 12, 12',
-            'or 5, 11, 11',
-            'or 6, 10, 10',
-            'or 7, 9, 9',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
-            'or 3, 17, 17',
-            'or 4, 16, 16',
-            'or 5, 15, 15',
-            'or 6, 14, 14',
-            'or 7, 18, 18',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *14, *8, *8',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.adde *3, *14, *8',
+            'sv.adde *17, *17, *38',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'or 16, 3, 3',
-            'or 15, 4, 4',
-            'or 14, 5, 5',
-            'or 12, 6, 6',
-            'or 11, 7, 7',
+            'or 35, 19, 19',
+            'or 36, 20, 20',
+            'or 37, 21, 21',
             'setvl 0, 0, 8, 0, 1, 1',
-            'or 3, 36, 36',
-            'or 4, 35, 35',
-            'or 5, 20, 20',
-            'or 6, 16, 16',
-            'or 7, 15, 15',
-            'or 8, 14, 14',
-            'or 9, 12, 12',
-            'or 10, 11, 11',
+            'or 14, 30, 30',
+            'or 15, 31, 31',
+            'or 16, 32, 32',
+            'or 19, 35, 35',
+            'or 20, 36, 36',
+            'or 21, 37, 37',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *37, *3, *3',
+            'sv.or *30, *14, *14',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 3, 47, 47',
+            'or 10, 43, 43',
             'setvl 0, 0, 1, 0, 1, 1',
-            'or 5, 3, 3',
+            'or 43, 10, 10',
             'addi 3, 0, 0',
-            'or 4, 3, 3',
             'setvl 0, 0, 1, 0, 1, 1',
-            'addi 3, 0, 0',
-            'or 6, 46, 46',
+            'addi 4, 0, 0',
+            'or 42, 48, 48',
+            'or 10, 43, 43',
+            'or 4, 3, 3',
             'setvl 0, 0, 1, 0, 1, 1',
-            'sv.maddedu *3, *6, 5, 4',
-            'or 5, 4, 4',
+            'sv.maddedu *3, *42, 10, 4',
             'setvl 0, 0, 1, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'or 4, 5, 5',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *35, *3, *3',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *3, *21, *21',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *17, *3, *3',
-            'or 4, 17, 17',
-            'or 16, 18, 18',
-            'or 15, 19, 19',
-            'or 14, 20, 20',
-            'or 12, 21, 21',
-            'or 11, 22, 22',
-            'or 10, 23, 23',
-            'or 3, 24, 24',
             'setvl 0, 0, 7, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 16, 16',
-            'or 5, 15, 15',
-            'or 6, 14, 14',
-            'or 7, 12, 12',
-            'or 8, 11, 11',
-            'or 9, 10, 10',
             'setvl 0, 0, 7, 0, 1, 1',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *28, *3, *3',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *3, *37, *37',
+            'sv.or *14, *30, *30',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or *17, *3, *3',
-            'or 4, 17, 17',
-            'or 16, 18, 18',
-            'or 15, 19, 19',
-            'or 14, 20, 20',
-            'or 12, 21, 21',
-            'or 11, 22, 22',
-            'or 10, 23, 23',
-            'or 3, 24, 24',
+            'or 30, 14, 14',
+            'or 31, 15, 15',
+            'or 32, 16, 16',
+            'or 35, 19, 19',
+            'or 36, 20, 20',
+            'or 37, 21, 21',
             'setvl 0, 0, 7, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 16, 16',
-            'or 5, 15, 15',
-            'or 6, 14, 14',
-            'or 7, 12, 12',
-            'or 8, 11, 11',
-            'or 9, 10, 10',
+            'or 14, 30, 30',
+            'or 15, 31, 31',
+            'or 16, 32, 32',
+            'or 19, 35, 35',
+            'or 20, 36, 36',
             'setvl 0, 0, 7, 0, 1, 1',
             'setvl 0, 0, 7, 0, 1, 1',
+            'sv.or *30, *14, *14',
             'setvl 0, 0, 7, 0, 1, 1',
             'subfc 0, 0, 0',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *21, *28, *28',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *14, *3, *3',
+            'sv.or *14, *30, *30',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.subfe *3, *21, *14',
+            'sv.subfe *30, *22, *14',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *3, *35, *35',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *5, *3, *3',
-            'or 4, 5, 5',
-            'or 11, 6, 6',
-            'addi 3, 0, 0',
-            'or 10, 3, 3',
+            'addi 10, 0, 0',
             'setvl 0, 0, 7, 0, 1, 1',
-            'or 3, 4, 4',
-            'or 4, 11, 11',
             'or 5, 10, 10',
             'or 6, 10, 10',
             'or 7, 10, 10',
@@ -1691,114 +1462,56 @@ class TestToomCook(unittest.TestCase):
             'setvl 0, 0, 7, 0, 1, 1',
             'subfc 0, 0, 0',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *21, *3, *3',
             'setvl 0, 0, 7, 0, 1, 1',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.subfe *3, *21, *14',
+            'sv.subfe *14, *3, *30',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *14, *3, *3',
             'setvl 0, 0, 7, 0, 1, 1',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *3, *28, *28',
             'setvl 0, 0, 7, 0, 1, 1',
-            'or 25, 3, 3',
-            'or 24, 4, 4',
-            'or 23, 5, 5',
-            'or 22, 6, 6',
-            'or 21, 7, 7',
-            'or 12, 8, 8',
-            'or 11, 9, 9',
             'setvl 0, 0, 7, 0, 1, 1',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or *3, *14, *14',
             'setvl 0, 0, 7, 0, 1, 1',
-            'sv.or/mrr *4, *3, *3',
-            'or 18, 4, 4',
-            'or 17, 5, 5',
-            'or 16, 6, 6',
-            'or 15, 7, 7',
-            'or 14, 8, 8',
-            'or 3, 9, 9',
-            'or 3, 10, 10',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *3, *35, *35',
             'setvl 0, 0, 2, 0, 1, 1',
-            'or 20, 3, 3',
-            'or 19, 4, 4',
-            'addi 3, 0, 0',
-            'addi 3, 0, 0',
-            'or 8, 3, 3',
+            'addi 10, 0, 0',
+            'addi 10, 0, 0',
+            'or 29, 10, 10',
             'setvl 0, 0, 5, 0, 1, 1',
-            'or 3, 22, 22',
-            'or 4, 21, 21',
-            'or 5, 12, 12',
-            'or 6, 11, 11',
-            'or 7, 8, 8',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
-            'or 3, 18, 18',
-            'or 4, 17, 17',
-            'or 5, 16, 16',
-            'or 6, 15, 15',
-            'or 7, 14, 14',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *14, *8, *8',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or *8, *3, *3',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.adde *3, *14, *8',
+            'sv.adde *25, *25, *14',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
             'setvl 0, 0, 5, 0, 1, 1',
-            'sv.or/mrr *4, *3, *3',
-            'or 16, 4, 4',
-            'or 15, 5, 5',
-            'or 14, 6, 6',
-            'or 3, 7, 7',
-            'or 5, 8, 8',
             'setvl 0, 0, 2, 0, 1, 1',
-            'or 4, 5, 5',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *5, *3, *3',
-            'or 3, 20, 20',
-            'or 4, 19, 19',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
             'addic 0, 0, 0',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *7, *5, *5',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.or *5, *3, *3',
             'setvl 0, 0, 2, 0, 1, 1',
-            'sv.adde *3, *7, *5',
+            'sv.adde *28, *28, *3',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
             'setvl 0, 0, 2, 0, 1, 1',
-            'or 12, 3, 3',
-            'or 11, 4, 4',
             'setvl 0, 0, 8, 0, 1, 1',
-            'or 3, 25, 25',
-            'or 4, 24, 24',
-            'or 5, 23, 23',
-            'or 6, 16, 16',
-            'or 7, 15, 15',
-            'or 8, 14, 14',
-            'or 9, 12, 12',
-            'or 10, 11, 11',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.or/mrr *4, *3, *3',
-            'or 3, 45, 45',
+            'or 3, 49, 49',
             'setvl 0, 0, 8, 0, 1, 1',
-            'sv.std *4, 0(3)',
+            'sv.std *22, 0(3)',
         ])
 
     def tst_toom_mul_sim(
diff --git a/src/bigint_presentation_code/register_allocator.py b/src/bigint_presentation_code/register_allocator.py
index 8dfdd58..959e1c3 100644
--- a/src/bigint_presentation_code/register_allocator.py
+++ b/src/bigint_presentation_code/register_allocator.py
@@ -438,14 +438,6 @@ class MergedSSAValToIGNodeMap(Mapping[MergedSSAVal, "IGNode"]):
         for n, edge in edges.items():
             if edge.copy_relation is None or not edge.interferes:
                 continue
-            try:
-                # if merging works, then the edge can't interfere
-                _ = final_merged_ssa_val.copy_merged(
-                    lhs_loc=loc, rhs=n.merged_ssa_val, rhs_loc=n.loc,
-                    copy_relation=edge.copy_relation)
-            except BadMergedSSAVal:
-                continue
-            edges[n] = replace(edge, interferes=False)
         retval = IGNode(
             node_id=self.__next_node_id, merged_ssa_val=final_merged_ssa_val,
             edges=edges, loc=loc, ignored=False)