From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 4 May 2016 05:03:04 +0000 (-0700)
Subject: Added GreenPak I/O buffer cells
X-Git-Tag: yosys-0.7~235^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66095153fd6110dbe84552175d4919f4f5fd75fc;p=yosys.git

Added GreenPak I/O buffer cells
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 7555a7ac8..a8bb538c4 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -134,6 +134,15 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q);
 	end
 endmodule
 
+module GP_IBUF(input IN, output OUT);
+	assign OUT = IN;
+endmodule
+
+module GP_IOBUF(input IN, input DIR, output OUT, inout IO);
+	assign IN = IO;
+	assign DIR = OE ? OUT : 1'bz;
+endmodule
+
 module GP_INV(input IN, output OUT);
 	assign OUT = ~IN;
 endmodule
@@ -161,6 +170,14 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
 	
 endmodule
 
+module GP_OBUF(input IN, output OUT);
+	assign OUT = IN;
+endmodule
+
+module GP_OBUFT(input IN, input OE, output OUT);
+	assign OUT = OE ? IN : 1'bz;
+endmodule
+
 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 
 	parameter GAIN = 1;