From: Sandipan Das Date: Sat, 6 Feb 2021 11:57:36 +0000 (+0530) Subject: arch-power: Add byte order attribute for PC state X-Git-Tag: develop-gem5-snapshot~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6617a38776393705ca2b56ac06a71271ea971226;p=gem5.git arch-power: Add byte order attribute for PC state This adds byte order as an attribute for PC state by introducing a new PCState class. The decoder can now fetch instructions bytes in the specified byte order in preparation for multi-mode support. Change-Id: I917333df88114a733cc5a8077cc420d5328f608b Signed-off-by: Sandipan Das --- diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh index 4e02ef7bc..c30014cce 100644 --- a/src/arch/power/decoder.hh +++ b/src/arch/power/decoder.hh @@ -67,7 +67,7 @@ class Decoder : public InstDecoder void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - emi = betoh(inst); + emi = gtoh(inst, pc.byteOrder()); instDone = true; } diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index a76e6e29f..c5a8f0fd1 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -32,6 +32,7 @@ #include "arch/generic/types.hh" #include "base/bitunion.hh" #include "base/types.hh" +#include "enums/ByteOrder.hh" namespace PowerISA { @@ -94,7 +95,40 @@ BitUnion32(ExtMachInst) Bitfield<19, 12> fxm; EndBitUnion(ExtMachInst) -typedef GenericISA::SimplePCState PCState; +class PCState : public GenericISA::SimplePCState +{ + private: + typedef GenericISA::SimplePCState Base; + ByteOrder guestByteOrder = ByteOrder::big; + + public: + PCState() + {} + + void + set(Addr val) + { + Base::set(val); + npc(val + sizeof(MachInst)); + } + + PCState(Addr val) + { + set(val); + } + + ByteOrder + byteOrder() const + { + return guestByteOrder; + } + + void + byteOrder(ByteOrder order) + { + guestByteOrder = order; + } +}; // typedef uint64_t LargestRead; // // Need to use 64 bits to make sure that read requests get handled properly