From: Brian Date: Sun, 20 Jan 2008 22:00:18 +0000 (-0700) Subject: Cell: use depth/stencil state to enable ztest X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=661be1ae7b1cd5837d8e7224a5ebe1b8d428137e;p=mesa.git Cell: use depth/stencil state to enable ztest Move z-test code into do_depth_test(). Add ZSIZE symbol to support 2 or 4-byte Z values. --- diff --git a/src/mesa/pipe/cell/spu/spu_main.c b/src/mesa/pipe/cell/spu/spu_main.c index bff098f06e9..30c39aab68d 100644 --- a/src/mesa/pipe/cell/spu/spu_main.c +++ b/src/mesa/pipe/cell/spu/spu_main.c @@ -239,8 +239,8 @@ cmd_render(const struct cell_command_render *render) /* how much vertex data */ vertex_bytes = render->num_verts * vertex_size; index_bytes = render->num_indexes * sizeof(ushort); - if (index_bytes < 8) - index_bytes = 8; + if (index_bytes < 16) + index_bytes = 16; else index_bytes = (index_bytes + 15) & ~0xf; /* multiple of 16 */ @@ -297,7 +297,7 @@ cmd_render(const struct cell_command_render *render) /* Start fetching color/z tiles. We'll wait for completion when * we need read/write to them later in triangle rasterization. */ - if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) { + if (spu.depth_stencil.depth.enabled) { if (tile_status_z[ty][tx] != TILE_STATUS_CLEAR) { get_tile(tx, ty, (uint *) ztile, TAG_READ_TILE_Z, 1); } @@ -325,7 +325,7 @@ cmd_render(const struct cell_command_render *render) put_tile(tx, ty, (uint *) ctile, TAG_WRITE_TILE_COLOR, 0); tile_status[ty][tx] = TILE_STATUS_DEFINED; } - if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) { + if (spu.depth_stencil.depth.enabled) { if (tile_status_z[ty][tx] == TILE_STATUS_DIRTY) { put_tile(tx, ty, (uint *) ztile, TAG_WRITE_TILE_Z, 1); tile_status_z[ty][tx] = TILE_STATUS_DEFINED; @@ -334,7 +334,7 @@ cmd_render(const struct cell_command_render *render) /* XXX move these... */ wait_on_mask(1 << TAG_WRITE_TILE_COLOR); - if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) { + if (spu.depth_stencil.depth.enabled) { wait_on_mask(1 << TAG_WRITE_TILE_Z); } } @@ -365,6 +365,14 @@ cmd_framebuffer(const struct cell_command_framebuffer *cmd) spu.fb.height = cmd->height; spu.fb.width_tiles = (spu.fb.width + TILE_SIZE - 1) / TILE_SIZE; spu.fb.height_tiles = (spu.fb.height + TILE_SIZE - 1) / TILE_SIZE; + + if (cmd->depth_format == PIPE_FORMAT_Z16_UNORM) { + ASSERT(ZSIZE == 2); + } + else if (cmd->depth_format == PIPE_FORMAT_Z32_UNORM) { + ASSERT(ZSIZE == 4); + } + } @@ -375,9 +383,9 @@ cmd_state_depth_stencil(const struct pipe_depth_stencil_alpha_state *state) printf("SPU %u: DEPTH_STENCIL: ztest %d\n", spu.init.id, state->depth.enabled); - /* + memcpy(&spu.depth_stencil, state, sizeof(*state)); - */ + } diff --git a/src/mesa/pipe/cell/spu/spu_main.h b/src/mesa/pipe/cell/spu/spu_main.h index f39f375d244..cd2afbe9bf1 100644 --- a/src/mesa/pipe/cell/spu/spu_main.h +++ b/src/mesa/pipe/cell/spu/spu_main.h @@ -32,6 +32,8 @@ #include "pipe/cell/common.h" #include "pipe/p_state.h" +/** XXX temp bytes/z value */ +#define ZSIZE 2 struct spu_framebuffer { void *color_start; /**< addr of color surface in main memory */ diff --git a/src/mesa/pipe/cell/spu/spu_tile.c b/src/mesa/pipe/cell/spu/spu_tile.c index 1505cb322b7..13fc5e345f4 100644 --- a/src/mesa/pipe/cell/spu/spu_tile.c +++ b/src/mesa/pipe/cell/spu/spu_tile.c @@ -32,7 +32,11 @@ uint ctile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#if ZSIZE == 2 ushort ztile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#else +uint ztile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#endif ubyte tile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB; ubyte tile_status_z[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB; @@ -43,7 +47,7 @@ void get_tile(uint tx, uint ty, uint *tile, int tag, int zBuf) { const uint offset = ty * spu.fb.width_tiles + tx; - const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? 2 : 4); + const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? ZSIZE : 4); const ubyte *src = zBuf ? spu.fb.depth_start : spu.fb.color_start; src += offset * bytesPerTile; @@ -68,7 +72,7 @@ void put_tile(uint tx, uint ty, const uint *tile, int tag, int zBuf) { const uint offset = ty * spu.fb.width_tiles + tx; - const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? 2 : 4); + const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? ZSIZE : 4); ubyte *dst = zBuf ? spu.fb.depth_start : spu.fb.color_start; dst += offset * bytesPerTile; @@ -81,7 +85,6 @@ put_tile(uint tx, uint ty, const uint *tile, int tag, int zBuf) spu.init.id, tile, (unsigned int) dst, bytesPerTile); */ - mfc_put((void *) tile, /* src in local memory */ (unsigned int) dst, /* dst in main memory */ bytesPerTile, @@ -103,7 +106,13 @@ clear_tile(uint tile[TILE_SIZE][TILE_SIZE], uint value) } void -clear_tile_z(ushort tile[TILE_SIZE][TILE_SIZE], uint value) +clear_tile_z( +#if ZSIZE == 2 + ushort tile[TILE_SIZE][TILE_SIZE], +#else + uint tile[TILE_SIZE][TILE_SIZE], +#endif + uint value) { uint i, j; for (i = 0; i < TILE_SIZE; i++) { diff --git a/src/mesa/pipe/cell/spu/spu_tile.h b/src/mesa/pipe/cell/spu/spu_tile.h index 637923764b9..7c288a1f915 100644 --- a/src/mesa/pipe/cell/spu/spu_tile.h +++ b/src/mesa/pipe/cell/spu/spu_tile.h @@ -40,7 +40,11 @@ extern uint ctile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#if ZSIZE == 2 extern ushort ztile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#else +extern uint ztile[TILE_SIZE][TILE_SIZE] ALIGN16_ATTRIB; +#endif #define TILE_STATUS_CLEAR 1 @@ -61,7 +65,13 @@ void clear_tile(uint tile[TILE_SIZE][TILE_SIZE], uint value); void -clear_tile_z(ushort tile[TILE_SIZE][TILE_SIZE], uint value); +clear_tile_z( +#if ZSIZE == 2 + ushort tile[TILE_SIZE][TILE_SIZE], +#else + uint tile[TILE_SIZE][TILE_SIZE], +#endif + uint value); #endif /* SPU_TILE_H */ diff --git a/src/mesa/pipe/cell/spu/spu_tri.c b/src/mesa/pipe/cell/spu/spu_tri.c index ddd5e662d2f..0b8533092e9 100644 --- a/src/mesa/pipe/cell/spu/spu_tri.c +++ b/src/mesa/pipe/cell/spu/spu_tri.c @@ -217,8 +217,8 @@ static INLINE void eval_z( struct setup_stage *setup, float x, float y, float result[4]) { - uint slot = 0; - uint i = 2; + const uint slot = 0; + const uint i = 2; const float *dadx = setup->coef[slot].dadx; const float *dady = setup->coef[slot].dady; @@ -252,6 +252,72 @@ pack_color(const float color[4]) } +static uint +do_depth_test(struct setup_stage *setup, int x, int y, unsigned mask) +{ + int ix = x - setup->cliprect_minx; + int iy = y - setup->cliprect_miny; + float zvals[4]; + float zscale = 65535.0; + + if (ZSIZE == 2) { + ASSERT(spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM); + } + else { + ASSERT(spu.fb.depth_format == PIPE_FORMAT_Z32_UNORM); + } + ASSERT(sizeof(ztile[0][0]) == ZSIZE); + + + eval_z(setup, (float) x, (float) y, zvals); + + if (tile_status_z[setup->ty][setup->tx] == TILE_STATUS_CLEAR) { + /* now, _really_ clear the tile */ + clear_tile_z(ztile, spu.fb.depth_clear_value); + } + else { + /* make sure we've got the tile from main mem */ + wait_on_mask(1 << TAG_READ_TILE_Z); + } + tile_status_z[setup->ty][setup->tx] = TILE_STATUS_DIRTY; + + + if (mask & MASK_TOP_LEFT) { + uint z = (uint) (zvals[0] * zscale); + if (z < ztile[iy][ix]) + ztile[iy][ix] = z; + else + mask &= ~MASK_TOP_LEFT; + } + + if (mask & MASK_TOP_RIGHT) { + uint z = (uint) (zvals[1] * zscale); + if (z < ztile[iy][ix+1]) + ztile[iy][ix+1] = z; + else + mask &= ~MASK_TOP_RIGHT; + } + + if (mask & MASK_BOTTOM_LEFT) { + uint z = (uint) (zvals[2] * zscale); + if (z < ztile[iy+1][ix]) + ztile[iy+1][ix] = z; + else + mask &= ~MASK_BOTTOM_LEFT; + } + + if (mask & MASK_BOTTOM_RIGHT) { + uint z = (uint) (zvals[3] * zscale); + if (z < ztile[iy+1][ix+1]) + ztile[iy+1][ix+1] = z; + else + mask &= ~MASK_BOTTOM_RIGHT; + } + + return mask; +} + + /** * Emit a quad (pass to next stage). No clipping is done. */ @@ -266,58 +332,14 @@ emit_quad( struct setup_stage *setup, int x, int y, unsigned mask ) sp->quad.first->run(sp->quad.first, &setup->quad); #else /* Cell: "write" quad fragments to the tile by setting prim color */ - int ix = x - setup->cliprect_minx; - int iy = y - setup->cliprect_miny; + const int ix = x - setup->cliprect_minx; + const int iy = y - setup->cliprect_miny; float colors[4][4]; - uint z; eval_coeff(setup, 1, (float) x, (float) y, colors); - if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) { - float zvals[4]; - eval_z(setup, (float) x, (float) y, zvals); - - if (tile_status_z[setup->ty][setup->tx] == TILE_STATUS_CLEAR) { - /* now, _really_ clear the tile */ - clear_tile_z(ztile, spu.fb.depth_clear_value); - } - else { - /* make sure we've got the tile from main mem */ - wait_on_mask(1 << TAG_READ_TILE_Z); - } - tile_status_z[setup->ty][setup->tx] = TILE_STATUS_DIRTY; - - if (mask & MASK_TOP_LEFT) { - z = (uint) (zvals[0] * 65535.0); - if (z < ztile[iy][ix]) - ztile[iy][ix] = z; - else - mask &= ~MASK_TOP_LEFT; - } - - if (mask & MASK_TOP_RIGHT) { - z = (uint) (zvals[1] * 65535.0); - if (z < ztile[iy][ix+1]) - ztile[iy][ix+1] = z; - else - mask &= ~MASK_TOP_RIGHT; - } - - if (mask & MASK_BOTTOM_LEFT) { - z = (uint) (zvals[2] * 65535.0); - if (z < ztile[iy+1][ix]) - ztile[iy+1][ix] = z; - else - mask &= ~MASK_BOTTOM_LEFT; - } - - if (mask & MASK_BOTTOM_RIGHT) { - z = (uint) (zvals[3] * 65535.0); - if (z < ztile[iy+1][ix+1]) - ztile[iy+1][ix+1] = z; - else - mask &= ~MASK_BOTTOM_RIGHT; - } + if (spu.depth_stencil.depth.enabled) { + mask &= do_depth_test(setup, x, y, mask); } if (mask) {