From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jun 2022 14:26:53 +0000 (+0100)
Subject: clarify primer
X-Git-Tag: opf_rfc_ls005_v1~1704
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=661f00ea3726c971df8a8acf3b8da713e07fdb37;p=libreriscv.git

clarify primer
---

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index a2fc94f0c..99fcd8b59 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -110,6 +110,9 @@ the number of instructions increase:
 	\item Documentation of the ISA
 	\item Manual coding and optimisation
 	\item Time to support the platform
+	\item Compilance Suite development and testing
+    \item Protracted Variable-Length encoding (x86) severely compromises
+          Multi-issue decoding
 \end{itemize}
 
 \subsection{Simple Vectorisation}
@@ -124,9 +127,9 @@ Main design principles
 \begin{itemize}
 	\item Introduce by implementing on top of existing Power ISA
 	\item Effectively a \textbf{hardware for-loop}, pauses main PC,
-	      issues multiple scalar op's
-	\item Preserves underlying scalar execution dependencies as
-	      the for-loop had been expanded as actual scalar instructions
+	      issues multiple scalar operations
+	\item Preserves underlying scalar execution dependencies as if
+	      the for-loop had been expanded into actual scalar instructions
         ("preserving Program Order")
 	\item Augments existing instructions by adding "tags" - provides
           Vectorisation "context" rather than adding new opcodes.
@@ -135,7 +138,8 @@ Main design principles
           advantage in the vector space (see \ref{subsubsec:add_to_pow_isa})
 	\item Aimed at Supercomputing: avoids creating significant
 	      \textit{sequential dependency hazards}, allowing \textbf{high
-	      performance superscalar microarchitectures} to be deployed.
+	      performance multi-issue superscalar microarchitectures} to be
+          leveraged.
 \end{itemize}
 
 Advantages include: