From: whitequark Date: Wed, 3 Jun 2020 16:00:40 +0000 (+0000) Subject: flatten: simplify. X-Git-Tag: working-ls180~495^2~4 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd;p=yosys.git flatten: simplify. Flattening does not benefit from topologically sorting cells within a module when processing them. --- diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index f37be685b..82e697495 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -260,10 +260,6 @@ struct FlattenWorker SigMap sigmap(module); - TopoSort> cells; - dict> cell_to_inbit; - dict> outbit_to_cell; - for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) @@ -279,37 +275,6 @@ struct FlattenWorker continue; } - for (auto &conn : cell->connections()) - { - RTLIL::SigSpec sig = sigmap(conn.second); - sig.remove_const(); - - if (GetSize(sig) == 0) - continue; - - RTLIL::Module *tpl = design->module(cell->type); - RTLIL::Wire *port = tpl->wire(conn.first); - if (port && port->port_input) - cell_to_inbit[cell].insert(sig.begin(), sig.end()); - if (port && port->port_output) - for (auto &bit : sig) - outbit_to_cell[bit].insert(cell); - } - - cells.node(cell); - } - - for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); - - cells.sort(); - - for (auto cell : cells.sorted) - { - log_assert(cell == module->cell(cell->name)); - RTLIL::Module *tpl = design->module(cell->type); dict parameters(cell->parameters);