From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 15:16:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~230
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=662d139d3395bd5b29fcc44807cb201b004b6169;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index abb3312a2..dc9324bb5 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -295,7 +295,12 @@ Answer:
 
 VL>1 at the moment, with a scalar source and scalar dest, will
 not undergo any changes to the EA compared to if VL=1.
-TBD
+Destination SPLAT if scalar is only influenced by predication
+which has a workaround below (merge to single bit mask)
+
+**LD/ST Indexed**
+
+TODO
 
 ## answers to 4, loops/uses
 
@@ -306,9 +311,21 @@ predicated element to the first **REMAPped** element, and combined
 with predication (single bit or otherwise) selection of a
 single element is achieved.
 
+(but hang on, does it actually? answer: no.  scalar sources are not REMAPped regardless of VL)
+
 biggest concern: how to achieve the same effect?
 
-answer: use at least one vector source.
+answer: use at least one vector source.  this solves the predication issue.
 
 question: does this impact LD/ST which has special overrides
 and mode-selection based on RA.isvec?
+
+**predication**
+
+with nonzeroing the application of a predicate mask to an all-scalar
+operation effectively tests **ALL** relevant bits 0..VL-1 as nonzero in the
+decision-making, whereas VL=1 will only test the first.
+
+a need for
+merging all bits into a single alternative predicate mask (single-bit)
+is the sort of thing we can probably live with.