From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 30 Sep 2020 09:19:00 +0000 (+0100)
Subject: halve the number of icache lines for now
X-Git-Tag: 24jan2021_ls180~276
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6630c04633f0ef3ceaaf21127234e8609d7e9e4c;p=soc.git

halve the number of icache lines for now
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 03c3f4a3..9481eb7f 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -60,7 +60,7 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 32
+NUM_LINES      = 16
 # Number of ways
 NUM_WAYS       = 4
 # L1 ITLB number of entries (direct mapped)