From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Jul 2022 01:24:33 +0000 (+0100)
Subject: add DCT/FFT column
X-Git-Tag: opf_rfc_ls005_v1~966
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=663b021cf79f245925492a88eb43b72ba0d50e6f;p=libreriscv.git

add DCT/FFT column
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 9ec4a8330..6b0d39063 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,14 +1,14 @@
 **ISA Comparison Table** - discussion and research at <https://bugs.libre-soc.org/show_bug.cgi?id=893>
 
-|ISA <br>name  |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint  |LDST <br> Fault-First|Data-dep<br> Fail-first|Pred-<br> Result|Matrix HW<br> support|
-|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|-----------------------|----------------|---------------------|
-|Draft SVP64   |5 (1)          |see (25)          |Scalable (2)         |yes                |yes                 |yes (3)              |no (4)                   |see (5)         |yes (6) |yes (7)              |yes (8)                |yes (9)         |yes (10)             |
-|VSX           |700+           |700+? (26)        |Packed SIMD          |no                 |no                  |no                   |yes (12)                 |yes             |no      |no                   |no                     |no              |yes (13)             |
-|NEON          |~250 (14)      |7088 (28)         |Packed SIMD          |no                 |no                  |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   |
-|SVE2          |~1000 (15)     |6040 (29)         |Predicated SIMD(16)  |no (16)            |yes                 |no                   |yes                      |yes             |no      |yes (7)              |no                     |no              |yes (33)             |
-|AVX512 (17)   |~1000s (18)    |7256 (30)         |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   |
-|RVV (19)      |~190 (20)      |~25000 (31)       |Scalable (21)        |yes                |yes                 |no                   |yes                      |yes (22)        |no      |yes                  |no                     |no              |no                   |
-|Aurora SX(23) |~200 (24)      |unknown (32)      |Scalable (25)        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                     |no              |?                    |
+|ISA <br>name  |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint  |LDST <br> Fault-First|Data-dep<br> Fail-first|Pred-<br> Result|Matrix HW<br> support|DCT/FFT HW<br? support |
+|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|-----------------------|----------------|---------------------|-----------------------|
+|Draft SVP64   |5 (1)          |see (25)          |Scalable (2)         |yes                |yes                 |yes (3)              |no (4)                   |see (5)         |yes (6) |yes (7)              |yes (8)                |yes (9)         |yes (10)             | yes(11)               |
+|VSX           |700+           |700+? (26)        |Packed SIMD          |no                 |no                  |no                   |yes (12)                 |yes             |no      |no                   |no                     |no              |yes (13)             | no                    |
+|NEON          |~250 (14)      |7088 (28)         |Packed SIMD          |no                 |no                  |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   | no                    |
+|SVE2          |~1000 (15)     |6040 (29)         |Predicated SIMD(16)  |no (16)            |yes                 |no                   |yes                      |yes             |no      |yes (7)              |no                     |no              |yes (33)             | no                    |
+|AVX512 (17)   |~1000s (18)    |7256 (30)         |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   | no                    |
+|RVV (19)      |~190 (20)      |~25000 (31)       |Scalable (21)        |yes                |yes                 |no                   |yes                      |yes (22)        |no      |yes                  |no                     |no              |no                   | no                    |
+|Aurora SX(23) |~200 (24)      |unknown (32)      |Scalable (25)        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                     |no              |?                    | no                    |
 
 * (1): plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
 * (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
@@ -19,7 +19,8 @@
 * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
 * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
 * (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
-* (10): Any non-power-of-two Matrices up to 127 FMACs (or other FMA-style op), full triple-loop Schedule.  Also DCT (Lee) and FFT Full (RADIX2) Triple-loops supported. See [[sv/remap]]
+* (10): Any non-power-of-two Matrices up to 127 FMACs (or other FMA-style op), full triple-loop Schedule. See [[sv/remap]]
+* (11): DCT (Lee) and FFT Full Triple-loops supported, RADIX2-only. Normally only found in VLIW DSPs (TI MSP30, Qualcom Hexagon). See [[sv/remap]]
 * (12): VSX's Vector Registers are mis-named: they are 100% PackedSIMD. AVX-512 is not a Vector ISA either.  See [Flynn's Taxonomy](https://en.wikipedia.org/wiki/Flynn%27s_taxonomy)
 * (13): Power ISA v3.1 contains "Matrix Multiply Assist" (MMA) which due to PackedSIMD is restricted to RADIX2 and requires inline assembler loop-unrolling for non-power-of-two Matrix dimensions
 * (14): difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions).