From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 2 Feb 2017 07:11:59 +0000 (-0800)
Subject: For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6642f8c745b320bdb7bab2470c62defb1b1bb9e2;p=riscv-isa-sim.git

For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN

Resolves #76
---

diff --git a/riscv/insn_template.h b/riscv/insn_template.h
index 0dd0aa1..07aa16b 100644
--- a/riscv/insn_template.h
+++ b/riscv/insn_template.h
@@ -4,5 +4,6 @@
 #include "mulhi.h"
 #include "softfloat.h"
 #include "internals.h"
+#include "specialize.h"
 #include "tracer.h"
 #include <assert.h>
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index f0bea9b..56c9c7a 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,4 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(f64(FRS2), f64(FRS1)) ? FRS1 : FRS2);
+WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
+if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
+  WRITE_FRD(defaultNaNF64UI);
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 33b2bc6..bf90356 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,4 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(f32(FRS2), f32(FRS1)) ? FRS1 : FRS2);
+WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
+if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
+  WRITE_FRD(defaultNaNF32UI);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index e22b6ea..2a1755e 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,4 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(f64(FRS1), f64(FRS2)) ? FRS1 : FRS2);
+WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
+if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
+  WRITE_FRD(defaultNaNF64UI);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 0ebb3a8..831a7a2 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,4 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(f32(FRS1), f32(FRS2)) ? FRS1 : FRS2);
+WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
+if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
+  WRITE_FRD(defaultNaNF32UI);
 set_fp_exceptions;