From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Dec 2021 01:08:11 +0000 (+0000)
Subject: whoops error in accessing icache.ibus which is an intermediary
X-Git-Tag: sv_maxu_works-initial~627
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6645c20c2378534adfe0266d680d62abc51527f7;p=openpower-isa.git

whoops error in accessing icache.ibus which is an intermediary
set of signals
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index cc91b75d..333bb117 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -483,7 +483,7 @@ class TestRunnerBase(FHDLTestCase):
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache.bus,
                                              default_mem, "DCACHE")))
-            sim.add_sync_process(wrap(wb_get(icache.ibus,
+            sim.add_sync_process(wrap(wb_get(icache.bus,
                                              default_mem, "ICACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):