From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 23:18:07 +0000 (-0700)
Subject: Remove Xilinx test
X-Git-Tag: working-ls180~1085^2~52
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66607845eccb2e3bc17b017c4f6b109aeaecdf77;p=yosys.git

Remove Xilinx test
---

diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index a717c54f1..16e5f40e1 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
 
 #design -load gate
 #stat
-
-##########
-
-design -load read
-design -copy-to model $__XILINX_SHREG_
-hierarchy -top shregmap_variable_test
-prep
-design -save gold
-
-simplemap t:$dff t:$dffe
-shregmap -tech xilinx
-
-#stat
-# show -width
-# write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__XILINX_SHREG_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-# design -load gold
-# stat
-
-# design -load gate
-# stat
-