From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 29 Jul 2019 23:05:44 +0000 (-0700)
Subject: RST -> RSTBRST for RAMB8BWER
X-Git-Tag: working-ls180~1176^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66806085db7d730c27a330e541f8aecbba3bd342;p=yosys.git

RST -> RSTBRST for RAMB8BWER
---

diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v
index c9b33af42..16fd15e74 100644
--- a/techlibs/xilinx/xc6s_brams_map.v
+++ b/techlibs/xilinx/xc6s_brams_map.v
@@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
 		.CLKBRDCLK(CLK2 ^ !CLKPOL2),
 		.ENBRDEN(A1EN),
 		.REGCEBREGCE(|1),
-		.RSTB(|0)
+		.RSTBRST(|0)
 	);
 endmodule
 
@@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
 			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
 			.ENBRDEN(|1),
 			.REGCEBREGCE(|0),
-			.RSTB(|0),
+			.RSTBRST(|0),
 			.WEBWEU(B1EN_2)
 		);
 	end else begin
@@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
 			.CLKBRDCLK(CLK3 ^ !CLKPOL3),
 			.ENBRDEN(|1),
 			.REGCEBREGCE(|0),
-			.RSTB(|0),
+			.RSTBRST(|0),
 			.WEBWEU(B1EN_2)
 		);
 	end endgenerate