From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 23:28:02 +0000 (-0800)
Subject: ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
X-Git-Tag: working-ls180~863^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6692e5d558e7c7277153b7a3bd1623af0e57405d;p=yosys.git

ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 6b6d2b56f..9514e65d9 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -57,6 +57,9 @@ code sigA sigB sigH
 		sigH.append(O[i]);
 	}
 	log_assert(nusers(O.extract_end(i)) <= 1);
+
+	if (sigH.empty())
+		reject;
 endcode
 
 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
@@ -328,6 +331,8 @@ arg argD argQ clock clock_pol
 
 code
 	dff = nullptr;
+	if (argQ.empty())
+		reject;
 	for (auto c : argQ.chunks()) {
 		if (!c.wire)
 			reject;