From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 8 May 2013 20:31:42 +0000 (+0200)
Subject: top: connect dvisampler DMA IRQs
X-Git-Tag: 24jan2021_ls180~2943
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66b4bae7c8c9c6442a1265566c5efc26e8652da8;p=litex.git

top: connect dvisampler DMA IRQs
---

diff --git a/top.py b/top.py
index f3ed0b94..604cd6fe 100644
--- a/top.py
+++ b/top.py
@@ -83,6 +83,8 @@ class SoC(Module):
 		"uart":			0,
 		"timer0":		1,
 		"minimac":		2,
+		"dvisampler0":  3,
+		"dvisampler1":  4,
 	}
 
 	def __init__(self, platform):
@@ -153,7 +155,8 @@ class SoC(Module):
 		# Interrupts
 		#
 		for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
-			self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
+			if hasattr(self, k):
+				self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
 
 		#
 		# Clocking