From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 19:39:17 +0000 (-0800)
Subject: Enable two inout tests
X-Git-Tag: working-ls180~1237^2~255
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66b5f5166b358ae7efebd278ad32cd05f3eb72be;p=yosys.git

Enable two inout tests
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index ad0e86d24..8a809e480 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -47,23 +47,21 @@ module abc9_test008_sub(input a, output b);
 assign b = ~a;
 endmodule
 
-// TODO
-//module abc9_test009(inout io, input oe);
-//reg latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch <= io;
-//assign io = oe ? ~latch : 1'bz;
-//endmodule
+module abc9_test009(inout io, input oe);
+reg latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+assign io = oe ? ~latch : 1'bz;
+endmodule
 
-// TODO
-//module abc9_test010(inout [7:0] io, input oe);
-//reg [7:0] latch;
-//always @(io or oe)
-//    if (!oe)
-//        latch <= io;
-//assign io = oe ? ~latch : 1'bz;
-//endmodule
+module abc9_test010(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+    if (!oe)
+        latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
 
 // TODO
 //module abc9_test011(inout [7:0] io, input oe);