From: Simon Dardis <simon.dardis@imgtec.com>
Date: Fri, 6 Nov 2015 11:59:20 +0000 (+0000)
Subject: Update loongson vector reductions.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66c5c67baffb2fa9fd9085c01f2811b07f0f7f60;p=gcc.git

Update loongson vector reductions.

2015-11-06  Simon Dardis  <simon.dardis@imgtec.com>

        * config/mips/loongson.md (vec_loongson_extract_lo_<mode>): New, extract
        low part to scalar.
        (reduc_uplus_<mode>): Remove.
        (reduc_plus_scal_<mode>): Rename from reduc_splus_<mode>, Use vec
        loongson_extract_lo_<mode>.
        (reduc_smax_scal_<mode>, reduc_smin_scal_<mode>): Rename from
        reduc_smax_<mode>, reduc_smax_<mode>, use vec
        loongson_extract_lo_<mode>.
        (reduc_umax_scal_<mode>, reduc_umin_scal_<mode>): Rename.

From-SVN: r229844
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0355c9eaafa..9adcd20d145 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2015-11-06  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* config/mips/loongson.md (vec_loongson_extract_lo_<mode>): New, extract
+	low part to scalar.
+	(reduc_uplus_<mode>): Remove.
+	(reduc_plus_scal_<mode>): Rename from reduc_splus_<mode>, Use vec
+	loongson_extract_lo_<mode>.
+	(reduc_smax_scal_<mode>, reduc_smin_scal_<mode>): Rename from
+	reduc_smax_<mode>, reduc_smax_<mode>, use vec
+	loongson_extract_lo_<mode>.
+	(reduc_umax_scal_<mode>, reduc_umin_scal_<mode>): Rename.
+
 2015-11-06  Richard Biener  <rguenther@suse.de>
 
 	* tree-vectorizer.h (struct _bb_vec_info): Add region_begin/end
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index 0b19bd7baf8..b8489ab5ab9 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -852,58 +852,66 @@
   "dsrl\t%0,%1,%2"
   [(set_attr "type" "fcvt")])
 
-(define_expand "reduc_uplus_<mode>"
-  [(match_operand:VWH 0 "register_operand" "")
-   (match_operand:VWH 1 "register_operand" "")]
+(define_insn "vec_loongson_extract_lo_<mode>"
+  [(set (match_operand:<V_inner> 0 "register_operand" "=r")
+        (vec_select:<V_inner>
+          (match_operand:VWHB 1 "register_operand" "f")
+          (parallel [(const_int 0)])))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
-{
-  mips_expand_vec_reduc (operands[0], operands[1], gen_add<mode>3);
-  DONE;
-})
+  "mfc1\t%0,%1"
+  [(set_attr "type" "mfc")])
 
-; ??? Given that we're not describing a widening reduction, we should
-; not have separate optabs for signed and unsigned.
-(define_expand "reduc_splus_<mode>"
-  [(match_operand:VWHB 0 "register_operand" "")
+(define_expand "reduc_plus_scal_<mode>"
+  [(match_operand:<V_inner> 0 "register_operand" "")
    (match_operand:VWHB 1 "register_operand" "")]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
-  emit_insn (gen_reduc_uplus_<mode>(operands[0], operands[1]));
+  rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
+  mips_expand_vec_reduc (tmp, operands[1], gen_add<mode>3);
+  emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
   DONE;
 })
 
-(define_expand "reduc_smax_<mode>"
-  [(match_operand:VWHB 0 "register_operand" "")
+(define_expand "reduc_smax_scal_<mode>"
+  [(match_operand:<V_inner> 0 "register_operand" "")
    (match_operand:VWHB 1 "register_operand" "")]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
-  mips_expand_vec_reduc (operands[0], operands[1], gen_smax<mode>3);
+  rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
+  mips_expand_vec_reduc (tmp, operands[1], gen_smax<mode>3);
+  emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
   DONE;
 })
 
-(define_expand "reduc_smin_<mode>"
-  [(match_operand:VWHB 0 "register_operand" "")
+(define_expand "reduc_smin_scal_<mode>"
+  [(match_operand:<V_inner> 0 "register_operand" "")
    (match_operand:VWHB 1 "register_operand" "")]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
-  mips_expand_vec_reduc (operands[0], operands[1], gen_smin<mode>3);
+  rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
+  mips_expand_vec_reduc (tmp, operands[1], gen_smin<mode>3);
+  emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
   DONE;
 })
 
-(define_expand "reduc_umax_<mode>"
-  [(match_operand:VB 0 "register_operand" "")
+(define_expand "reduc_umax_scal_<mode>"
+  [(match_operand:<V_inner> 0 "register_operand" "")
    (match_operand:VB 1 "register_operand" "")]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
-  mips_expand_vec_reduc (operands[0], operands[1], gen_umax<mode>3);
+  rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
+  mips_expand_vec_reduc (tmp, operands[1], gen_umax<mode>3);
+  emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
   DONE;
 })
 
-(define_expand "reduc_umin_<mode>"
-  [(match_operand:VB 0 "register_operand" "")
+(define_expand "reduc_umin_scal_<mode>"
+  [(match_operand:<V_inner> 0 "register_operand" "")
    (match_operand:VB 1 "register_operand" "")]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
 {
-  mips_expand_vec_reduc (operands[0], operands[1], gen_umin<mode>3);
+  rtx tmp = gen_reg_rtx (GET_MODE (operands[1]));
+  mips_expand_vec_reduc (tmp, operands[1], gen_umin<mode>3);
+  emit_insn (gen_vec_loongson_extract_lo_<mode> (operands[0], tmp));
   DONE;
 })