From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 Feb 2019 21:21:52 +0000 (+0000)
Subject: doh! use z mantissa width to specify product width.
X-Git-Tag: ls180-24jan2020~1882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66cb3b90e9337d28936849ae937e5507ee4ca54f;p=ieee754fpu.git

doh! use z mantissa width to specify product width.
also take out hard-coded numbers, ready for 64 bit
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 1e02fa87..d5c3a830 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -24,7 +24,7 @@ class FPMUL(FPBase):
         b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
-        mw = (self.width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
 
         of = Overflow()
@@ -103,12 +103,13 @@ class FPMUL(FPBase):
 
             #multiply_1
             with m.State("multiply_1"):
+                mw = z.m.m_width
                 m.next = "normalise_1"
                 m.d.sync += [
-                z.m.eq(product[26:50]),
-                of.guard.eq(product[25]),
-                of.round_bit.eq(product[24]),
-                of.sticky.eq(product[0:23] != 0)
+                z.m.eq(product[mw+3:]),
+                of.guard.eq(product[mw+2]),
+                of.round_bit.eq(product[mw+1]),
+                of.sticky.eq(product[0:mw] != 0)
             ]
 
             # ******