From: lkcl <lkcl@web>
Date: Mon, 10 Apr 2023 21:33:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66d7749f4d2446f2eedb4a21a2454871cf3d369c;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index aeddefd60..8f6e8aa27 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -49,7 +49,8 @@ a result.  simple, saturate and pred-result are however inter-element
 independent and may easily be parallelised to give high performance,
 regardless of the value of VL.
 
-The Mode table for Arithmetic and Logical operations is laid out as
+The Mode table for Arithmetic and Logical operations,
+bring bits 19-23 of SVP64 `RM`, is laid out as
 follows:
 
 | 0-1 |  2  |  3   4  |  description              |