From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 May 2020 17:13:38 +0000 (+0100)
Subject: add comment about CMP swapping
X-Git-Tag: div_pipeline~1228
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66db5471307c031ce95e84aba93150794da0fa1f;p=soc.git

add comment about CMP swapping
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index ad4e8e87..3d5a3f45 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -48,6 +48,10 @@ class ALUMainStage(PipeModBase):
         with m.Switch(self.i.ctx.op.insn_type):
             #### CMP, CMPL ####
             with m.Case(InternalOp.OP_CMP):
+                # this is supposed to be inverted (b-a, not a-b)
+                # however we have a trick: instead of adding either 2x 64-bit
+                # MUXes to invert a and b, or messing with a 64-bit output,
+                # swap +ve and -ve test in the *output* stage using an XOR gate
                 comb += o.eq(add_output[1:-1])
 
             #### add ####