From: Luke Kenneth Casson Leighton Date: Tue, 21 May 2019 22:59:53 +0000 (+0100) Subject: working on all cycles, RaW / WaR X-Git-Tag: div_pipeline~2001 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=66f3fbb2912cba3ddafae8bc6fdee107e5d3f60e;p=soc.git working on all cycles, RaW / WaR --- diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index cab033be..9e17b3f2 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -417,8 +417,6 @@ def scoreboard_sim(dut, alusim): yield yield from print_reg(dut, [1,2,3]) yield - yield - yield yield yield from print_reg(dut, [1,2,3]) diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 9a54e3a4..649b44e2 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -51,7 +51,7 @@ class DepCell(Elaboratable): m.d.comb += l.r.eq(self.go_i) # Function Unit "Forward Progress". - m.d.comb += self.fwd_o.eq((cq | l.q) & self.hazard_i & ~self.issue_i) + m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i)# & ~self.issue_i) # Register Select. Activated on go read/write and *current* latch set m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)