From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 21:01:38 +0000 (+0200)
Subject: Add specify support to README
X-Git-Tag: yosys-0.9~141^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67005633e246e47683b11e13f08afb788bc9de02;p=yosys.git

Add specify support to README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/README.md b/README.md
index 913777f2e..d21d60c97 100644
--- a/README.md
+++ b/README.md
@@ -424,6 +424,11 @@ Verilog Attributes and non-standard features
   in an unconditional context (only if/case statements on parameters
   and constant values). The intended use for this is synthesis-time DRC.
 
+- There is limited support for converting specify .. endspecify statements to
+  special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
+  blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
+  functionality. (By default specify .. endspecify blocks are ignored.)
+
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================