From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 May 2021 11:58:15 +0000 (+0100)
Subject: match up PLL names
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=670638591d786b042f85f3839c59eb92e34ba1e6;p=libresoc-litex.git

match up PLL names
---

diff --git a/libresoc/core.py b/libresoc/core.py
index f58a6fb..35aac19 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -272,7 +272,7 @@ class LibreSoC(CPU):
         if "ls180" in variant and "pll" not in variant:
             self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
-            self.pll_ana_o = Signal()
+            self.pll_test_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
             self.cpu_params['o_pll_test_o'] = self.pll_test_o