From: Anouk Van Laer Date: Mon, 3 Sep 2018 11:17:27 +0000 (+0100) Subject: arch-arm: Added TLBI_ALL EL2 instruction X-Git-Tag: v19.0.0.0~1270 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=671840615bb721b9545789555e796f5d47a15bf6;p=gem5.git arch-arm: Added TLBI_ALL EL2 instruction This patch is adding TLBI_ALLE2(IS) operations to the arm ISA. Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011 Signed-off-by: Giacomo Travaglini Reviewed-by: Anouk Van Laer Reviewed-on: https://gem5-review.googlesource.com/c/15616 Reviewed-by: Nikos Nikoleris Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d7d51b887..17c87ba84 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1338,9 +1338,17 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tlbiOp.broadcast(tc); return; } - // @todo: uncomment this to enable Virtualization - // case MISCREG_TLBI_ALLE2IS: - // case MISCREG_TLBI_ALLE2: + // AArch64 TLB Invalidate All, EL2, Inner Shareable + case MISCREG_TLBI_ALLE2: + case MISCREG_TLBI_ALLE2IS: + { + assert64(tc); + scr = readMiscReg(MISCREG_SCR, tc); + + TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); + tlbiOp(tc); + return; + } // AArch64 TLB Invalidate All, EL1 case MISCREG_TLBI_ALLE1: case MISCREG_TLBI_VMALLE1: