From: Michael LeBeane <Michael.Lebeane@amd.com>
Date: Thu, 7 Jun 2018 20:49:26 +0000 (-0400)
Subject: arch-gcn3: Fix VOP2 dissasembly prints
X-Git-Tag: v20.1.0.0~471
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6747b127afa0c9ff4be3e147fbadd1be4e2bf491;p=gem5.git

arch-gcn3: Fix VOP2 dissasembly prints

VOP2 prints VSRC1 register index as hex instead of decimal if the
instruction contains a literal operand.  This patch resets the
format specifiers in the stream to print the register correctly.

Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
---

diff --git a/src/arch/gcn3/insts/op_encodings.cc b/src/arch/gcn3/insts/op_encodings.cc
index 2eb404253..fe501f215 100644
--- a/src/arch/gcn3/insts/op_encodings.cc
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -763,7 +763,8 @@ namespace Gcn3ISA
                        << extData.imm_u32 << ", ";
         }
 
-        dis_stream << "v" << instData.VSRC1;
+        dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
+            << instData.VSRC1;
 
         if (readsVCC())
             dis_stream << ", vcc";