From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700)
Subject: split out instructions from openpower/isa/fixedstore.mdwn
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=674de5c2298448cef36f4cd6ffe72c5241dd3f63;p=openpower-isa.git

split out instructions from openpower/isa/fixedstore.mdwn
---

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 161a06fc..5d68a57a 100644
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -14,371 +14,44 @@
 
 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
 
-# Store Byte
+[[!inline pagenames="openpower/isa/fixedstore/stb" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedstore/stbx" raw="yes"]]
 
-* stb RS,D(RA)
+[[!inline pagenames="openpower/isa/fixedstore/stbu" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedstore/stbux" raw="yes"]]
 
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+[[!inline pagenames="openpower/isa/fixedstore/sth" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedstore/sthx" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedstore/sthu" raw="yes"]]
 
-# Store Byte Indexed
+[[!inline pagenames="openpower/isa/fixedstore/sthux" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fixedstore/stw" raw="yes"]]
 
-* stbx RS,RA,RB
+[[!inline pagenames="openpower/isa/fixedstore/stwx" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedstore/stwu" raw="yes"]]
 
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+[[!inline pagenames="openpower/isa/fixedstore/stwux" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedstore/std" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedstore/stdx" raw="yes"]]
 
-# Store Byte with Update
+[[!inline pagenames="openpower/isa/fixedstore/stdu" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedstore/stdux" raw="yes"]]
 
-* stbu RS,D(RA)
+[[!inline pagenames="openpower/isa/fixedstore/stq" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedstore/sthbrx" raw="yes"]]
 
-    EA <- (RA) + EXTS(D)
-    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
-    RA <- EA
+[[!inline pagenames="openpower/isa/fixedstore/stwbrx" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedstore/stdbrx" raw="yes"]]
 
-    None
-
-# Store Byte with Update Indexed
-
-X-Form
-
-* stbux RS,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Store Halfword
-
-D-Form
-
-* sth RS,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Store Halfword Indexed
-
-X-Form
-
-* sthx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Store Halfword with Update
-
-D-Form
-
-* sthu RS,D(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(D)
-    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Store Halfword with Update Indexed
-
-X-Form
-
-* sthux RS,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Store Word
-
-D-Form
-
-* stw RS,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Store Word Indexed
-
-X-Form
-
-* stwx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Store Word with Update
-
-D-Form
-
-* stwu RS,D(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(D)
-    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Store Word with Update Indexed
-
-X-Form
-
-* stwux RS,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-
-
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
-
-# Store Doubleword
-
-DS-Form
-
-* std RS,DS(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(DS || 0b00)
-    MEM(EA, 8) <- (RS)
-
-Special Registers Altered:
-
-    None
-
-# Store Doubleword Indexed
-
-X-Form
-
-* stdx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 8) <- (RS)
-
-Special Registers Altered:
-
-    None
-
-# Store Doubleword with Update
-
-DS-Form
-
-* stdu RS,DS(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(DS || 0b00)
-    MEM(EA, 8) <- (RS)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Store Doubleword with Update Indexed
-
-X-Form
-
-* stdux RS,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    MEM(EA, 8) <- (RS)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-
-<!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
-<!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
-<!-- GPR is stored into the doubleword in storage addressed by EA and the -->
-<!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
-<!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
-<!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
-<!-- byte-reversed into the doubleword addressed by EA. -->
-
-
-# Store Quadword
-
-DS-Form
-
-* stq RSp,DS(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(DS || 0b00)
-    MEM(EA, 16) <- RSp
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-
-# Store Halfword Byte-Reverse Indexed
-
-X-Form
-
-* sthbrx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
-
-Special Registers Altered:
-
-    None
-
-# Store Word Byte-Reverse Indexed
-
-X-Form
-
-* stwbrx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
-                   ||(RS)[32:39])
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-
-# Store Doubleword Byte-Reverse Indexed
-
-X-Form
-
-* stdbrx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
-                    || (RS)[40:47] || (RS)[32:39]
-                    || (RS)[24:31] || (RS)[16:23]
-                    || (RS)[8:15]  || (RS)[0:7])
-
-Special Registers Altered:
-
-    None
-
-
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-# Store Multiple Word
-
-D-Form
-
-* stmw RS,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    r <- RS[0:63]
-    do while r <= 31
-        MEM(EA, 4) <- GPR(r)[32:63]
-        r <-  r + 1
-        EA <-  EA + 4
-
-Special Registers Altered:
-
-    None
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/fixedstore/stmw" raw="yes"]]
diff --git a/openpower/isa/fixedstore/stb.mdwn b/openpower/isa/fixedstore/stb.mdwn
new file mode 100644
index 00000000..70de6541
--- /dev/null
+++ b/openpower/isa/fixedstore/stb.mdwn
@@ -0,0 +1,13 @@
+# Store Byte
+
+D-Form
+
+* stb RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stb_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stb_code.mdwn b/openpower/isa/fixedstore/stb_code.mdwn
new file mode 100644
index 00000000..26967273
--- /dev/null
+++ b/openpower/isa/fixedstore/stb_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
diff --git a/openpower/isa/fixedstore/stbu.mdwn b/openpower/isa/fixedstore/stbu.mdwn
new file mode 100644
index 00000000..5d2fe922
--- /dev/null
+++ b/openpower/isa/fixedstore/stbu.mdwn
@@ -0,0 +1,13 @@
+# Store Byte with Update
+
+D-Form
+
+* stbu RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stbu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stbu_code.mdwn b/openpower/isa/fixedstore/stbu_code.mdwn
new file mode 100644
index 00000000..3dd00c07
--- /dev/null
+++ b/openpower/isa/fixedstore/stbu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stbux.mdwn b/openpower/isa/fixedstore/stbux.mdwn
new file mode 100644
index 00000000..a4b8ea30
--- /dev/null
+++ b/openpower/isa/fixedstore/stbux.mdwn
@@ -0,0 +1,13 @@
+# Store Byte with Update Indexed
+
+X-Form
+
+* stbux RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stbux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stbux_code.mdwn b/openpower/isa/fixedstore/stbux_code.mdwn
new file mode 100644
index 00000000..d99e79e2
--- /dev/null
+++ b/openpower/isa/fixedstore/stbux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stbx.mdwn b/openpower/isa/fixedstore/stbx.mdwn
new file mode 100644
index 00000000..ee766f5b
--- /dev/null
+++ b/openpower/isa/fixedstore/stbx.mdwn
@@ -0,0 +1,13 @@
+# Store Byte Indexed
+
+X-Form
+
+* stbx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stbx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stbx_code.mdwn b/openpower/isa/fixedstore/stbx_code.mdwn
new file mode 100644
index 00000000..7a2f6ed7
--- /dev/null
+++ b/openpower/isa/fixedstore/stbx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
diff --git a/openpower/isa/fixedstore/std.mdwn b/openpower/isa/fixedstore/std.mdwn
new file mode 100644
index 00000000..ae444307
--- /dev/null
+++ b/openpower/isa/fixedstore/std.mdwn
@@ -0,0 +1,13 @@
+# Store Doubleword
+
+DS-Form
+
+* std RS,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/std_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/std_code.mdwn b/openpower/isa/fixedstore/std_code.mdwn
new file mode 100644
index 00000000..8f9c591b
--- /dev/null
+++ b/openpower/isa/fixedstore/std_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(DS || 0b00)
+    MEM(EA, 8) <- (RS)
diff --git a/openpower/isa/fixedstore/stdbrx.mdwn b/openpower/isa/fixedstore/stdbrx.mdwn
new file mode 100644
index 00000000..b76ab70e
--- /dev/null
+++ b/openpower/isa/fixedstore/stdbrx.mdwn
@@ -0,0 +1,16 @@
+# Store Doubleword Byte-Reverse Indexed
+
+X-Form
+
+* stdbrx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stdbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+
+<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
diff --git a/openpower/isa/fixedstore/stdbrx_code.mdwn b/openpower/isa/fixedstore/stdbrx_code.mdwn
new file mode 100644
index 00000000..8678e3f1
--- /dev/null
+++ b/openpower/isa/fixedstore/stdbrx_code.mdwn
@@ -0,0 +1,6 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
+                    || (RS)[40:47] || (RS)[32:39]
+                    || (RS)[24:31] || (RS)[16:23]
+                    || (RS)[8:15]  || (RS)[0:7])
diff --git a/openpower/isa/fixedstore/stdu.mdwn b/openpower/isa/fixedstore/stdu.mdwn
new file mode 100644
index 00000000..e239b270
--- /dev/null
+++ b/openpower/isa/fixedstore/stdu.mdwn
@@ -0,0 +1,13 @@
+# Store Doubleword with Update
+
+DS-Form
+
+* stdu RS,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stdu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stdu_code.mdwn b/openpower/isa/fixedstore/stdu_code.mdwn
new file mode 100644
index 00000000..07489a38
--- /dev/null
+++ b/openpower/isa/fixedstore/stdu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(DS || 0b00)
+    MEM(EA, 8) <- (RS)
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stdux.mdwn b/openpower/isa/fixedstore/stdux.mdwn
new file mode 100644
index 00000000..93aa7d95
--- /dev/null
+++ b/openpower/isa/fixedstore/stdux.mdwn
@@ -0,0 +1,25 @@
+# Store Doubleword with Update Indexed
+
+X-Form
+
+* stdux RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stdux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+
+<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
+
+<!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
+<!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
+<!-- GPR is stored into the doubleword in storage addressed by EA and the -->
+<!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
+<!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
+<!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
+<!-- byte-reversed into the doubleword addressed by EA. -->
+
diff --git a/openpower/isa/fixedstore/stdux_code.mdwn b/openpower/isa/fixedstore/stdux_code.mdwn
new file mode 100644
index 00000000..eb2e923a
--- /dev/null
+++ b/openpower/isa/fixedstore/stdux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    MEM(EA, 8) <- (RS)
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stdx.mdwn b/openpower/isa/fixedstore/stdx.mdwn
new file mode 100644
index 00000000..abb9f0e5
--- /dev/null
+++ b/openpower/isa/fixedstore/stdx.mdwn
@@ -0,0 +1,13 @@
+# Store Doubleword Indexed
+
+X-Form
+
+* stdx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stdx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stdx_code.mdwn b/openpower/isa/fixedstore/stdx_code.mdwn
new file mode 100644
index 00000000..444bfe19
--- /dev/null
+++ b/openpower/isa/fixedstore/stdx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 8) <- (RS)
diff --git a/openpower/isa/fixedstore/sth.mdwn b/openpower/isa/fixedstore/sth.mdwn
new file mode 100644
index 00000000..fe67dd8c
--- /dev/null
+++ b/openpower/isa/fixedstore/sth.mdwn
@@ -0,0 +1,13 @@
+# Store Halfword
+
+D-Form
+
+* sth RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/sth_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/sth_code.mdwn b/openpower/isa/fixedstore/sth_code.mdwn
new file mode 100644
index 00000000..33bd6f3b
--- /dev/null
+++ b/openpower/isa/fixedstore/sth_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
diff --git a/openpower/isa/fixedstore/sthbrx.mdwn b/openpower/isa/fixedstore/sthbrx.mdwn
new file mode 100644
index 00000000..c3512a98
--- /dev/null
+++ b/openpower/isa/fixedstore/sthbrx.mdwn
@@ -0,0 +1,13 @@
+# Store Halfword Byte-Reverse Indexed
+
+X-Form
+
+* sthbrx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/sthbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/sthbrx_code.mdwn b/openpower/isa/fixedstore/sthbrx_code.mdwn
new file mode 100644
index 00000000..e5828149
--- /dev/null
+++ b/openpower/isa/fixedstore/sthbrx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
diff --git a/openpower/isa/fixedstore/sthu.mdwn b/openpower/isa/fixedstore/sthu.mdwn
new file mode 100644
index 00000000..42734381
--- /dev/null
+++ b/openpower/isa/fixedstore/sthu.mdwn
@@ -0,0 +1,13 @@
+# Store Halfword with Update
+
+D-Form
+
+* sthu RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/sthu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/sthu_code.mdwn b/openpower/isa/fixedstore/sthu_code.mdwn
new file mode 100644
index 00000000..ab7758d8
--- /dev/null
+++ b/openpower/isa/fixedstore/sthu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/sthux.mdwn b/openpower/isa/fixedstore/sthux.mdwn
new file mode 100644
index 00000000..a37d8952
--- /dev/null
+++ b/openpower/isa/fixedstore/sthux.mdwn
@@ -0,0 +1,13 @@
+# Store Halfword with Update Indexed
+
+X-Form
+
+* sthux RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/sthux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/sthux_code.mdwn b/openpower/isa/fixedstore/sthux_code.mdwn
new file mode 100644
index 00000000..78a2d786
--- /dev/null
+++ b/openpower/isa/fixedstore/sthux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/sthx.mdwn b/openpower/isa/fixedstore/sthx.mdwn
new file mode 100644
index 00000000..d178ecb7
--- /dev/null
+++ b/openpower/isa/fixedstore/sthx.mdwn
@@ -0,0 +1,13 @@
+# Store Halfword Indexed
+
+X-Form
+
+* sthx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/sthx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/sthx_code.mdwn b/openpower/isa/fixedstore/sthx_code.mdwn
new file mode 100644
index 00000000..ce8c6ef2
--- /dev/null
+++ b/openpower/isa/fixedstore/sthx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
diff --git a/openpower/isa/fixedstore/stmw.mdwn b/openpower/isa/fixedstore/stmw.mdwn
new file mode 100644
index 00000000..77fccf5f
--- /dev/null
+++ b/openpower/isa/fixedstore/stmw.mdwn
@@ -0,0 +1,15 @@
+# Store Multiple Word
+
+D-Form
+
+* stmw RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stmw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Checked March 2021 -->
diff --git a/openpower/isa/fixedstore/stmw_code.mdwn b/openpower/isa/fixedstore/stmw_code.mdwn
new file mode 100644
index 00000000..ea3022dc
--- /dev/null
+++ b/openpower/isa/fixedstore/stmw_code.mdwn
@@ -0,0 +1,7 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    r <- RS[0:63]
+    do while r <= 31
+        MEM(EA, 4) <- GPR(r)[32:63]
+        r <-  r + 1
+        EA <-  EA + 4
diff --git a/openpower/isa/fixedstore/stq.mdwn b/openpower/isa/fixedstore/stq.mdwn
new file mode 100644
index 00000000..3d6d3699
--- /dev/null
+++ b/openpower/isa/fixedstore/stq.mdwn
@@ -0,0 +1,15 @@
+# Store Quadword
+
+DS-Form
+
+* stq RSp,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stq_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
diff --git a/openpower/isa/fixedstore/stq_code.mdwn b/openpower/isa/fixedstore/stq_code.mdwn
new file mode 100644
index 00000000..a5495342
--- /dev/null
+++ b/openpower/isa/fixedstore/stq_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(DS || 0b00)
+    MEM(EA, 16) <- RSp
diff --git a/openpower/isa/fixedstore/stw.mdwn b/openpower/isa/fixedstore/stw.mdwn
new file mode 100644
index 00000000..62ad1c0e
--- /dev/null
+++ b/openpower/isa/fixedstore/stw.mdwn
@@ -0,0 +1,13 @@
+# Store Word
+
+D-Form
+
+* stw RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stw_code.mdwn b/openpower/isa/fixedstore/stw_code.mdwn
new file mode 100644
index 00000000..0bd2a7b6
--- /dev/null
+++ b/openpower/isa/fixedstore/stw_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
diff --git a/openpower/isa/fixedstore/stwbrx.mdwn b/openpower/isa/fixedstore/stwbrx.mdwn
new file mode 100644
index 00000000..145ee62a
--- /dev/null
+++ b/openpower/isa/fixedstore/stwbrx.mdwn
@@ -0,0 +1,15 @@
+# Store Word Byte-Reverse Indexed
+
+X-Form
+
+* stwbrx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stwbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
diff --git a/openpower/isa/fixedstore/stwbrx_code.mdwn b/openpower/isa/fixedstore/stwbrx_code.mdwn
new file mode 100644
index 00000000..2d853015
--- /dev/null
+++ b/openpower/isa/fixedstore/stwbrx_code.mdwn
@@ -0,0 +1,4 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
+                   ||(RS)[32:39])
diff --git a/openpower/isa/fixedstore/stwu.mdwn b/openpower/isa/fixedstore/stwu.mdwn
new file mode 100644
index 00000000..037323ec
--- /dev/null
+++ b/openpower/isa/fixedstore/stwu.mdwn
@@ -0,0 +1,13 @@
+# Store Word with Update
+
+D-Form
+
+* stwu RS,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stwu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stwu_code.mdwn b/openpower/isa/fixedstore/stwu_code.mdwn
new file mode 100644
index 00000000..135baa8f
--- /dev/null
+++ b/openpower/isa/fixedstore/stwu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stwux.mdwn b/openpower/isa/fixedstore/stwux.mdwn
new file mode 100644
index 00000000..2548f95a
--- /dev/null
+++ b/openpower/isa/fixedstore/stwux.mdwn
@@ -0,0 +1,17 @@
+# Store Word with Update Indexed
+
+X-Form
+
+* stwux RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stwux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+
+
+<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
diff --git a/openpower/isa/fixedstore/stwux_code.mdwn b/openpower/isa/fixedstore/stwux_code.mdwn
new file mode 100644
index 00000000..d97c34c2
--- /dev/null
+++ b/openpower/isa/fixedstore/stwux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
+    RA <- EA
diff --git a/openpower/isa/fixedstore/stwx.mdwn b/openpower/isa/fixedstore/stwx.mdwn
new file mode 100644
index 00000000..195cbc67
--- /dev/null
+++ b/openpower/isa/fixedstore/stwx.mdwn
@@ -0,0 +1,13 @@
+# Store Word Indexed
+
+X-Form
+
+* stwx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedstore/stwx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedstore/stwx_code.mdwn b/openpower/isa/fixedstore/stwx_code.mdwn
new file mode 100644
index 00000000..9921d5ad
--- /dev/null
+++ b/openpower/isa/fixedstore/stwx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]