From: programmerjake Date: Thu, 22 Dec 2022 19:58:29 +0000 (+0000) Subject: clarify bf16 vs fp16 X-Git-Tag: opf_rfc_ls005_v1~9 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=674ea72e5fb3aae98d97bd19c883e183b7d0f677;p=libreriscv.git clarify bf16 vs fp16 --- diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn index f449ff4f9..ac1870cb5 100644 --- a/openpower/sv/rfc/ls005.mdwn +++ b/openpower/sv/rfc/ls005.mdwn @@ -105,10 +105,12 @@ the FP width". "half width" exactly as presently defined. * XLEN=32 overrides FPR "full width" operations to full FP32, and "half width" to be "FP16 stored in an FP32" -* XLEN=16 redefines FPR "full width" operations to full BFP16 and leaves - "half width" UNDEFINED (there is no FP8). -* XLEN=8 redefines FPR "full width" operations to BF16 and leaves - "half width" UNDEFINED (there is no BF8). +* XLEN=16 redefines FPR "full width" operations to full [IEEE FP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves + "half width" UNDEFINED (there is no IEEE FP8). +* XLEN=8 redefines FPR "full width" operations to [BF16 (bfloat16)](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves + "half width" UNDEFINED[^1]. Note this means FPRs are 16 bits, not 8. + +[^1]: BF8 is very rarely used, though it does exist as the MSB half of IEEE FP16 ----------------