From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Tue, 1 May 2018 00:03:50 +0000 (-0700)
Subject: [rv64ua/lrsc] Initialize memory read out. (#135)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67500e2f200619bcd8ca3a8e5d396ea3021a7e27;p=riscv-tests.git

[rv64ua/lrsc] Initialize memory read out. (#135)

* [rv64ua/lrsc] Initialize memory read out.

Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.

* [rv64ua/lrsc] Use .skip instead of .align.
---

diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S
index 11eb7de..14ef07d 100644
--- a/isa/rv64ua/lrsc.S
+++ b/isa/rv64ua/lrsc.S
@@ -35,7 +35,7 @@ TEST_CASE( 2, a4, 1, \
 # TODO is this actually mandatory behavior?
 TEST_CASE( 3, a4, 1, \
   la a0, foo; \
-  add a1, a0, 1024; \
+  la a1, fooTest3; \
   lr.w a1, (a1); \
   sc.w a4, a1, (a0); \
 )
@@ -82,4 +82,6 @@ RVTEST_DATA_BEGIN
 coreid: .word 0
 barrier: .word 0
 foo: .word 0
+.skip 1024
+fooTest3: .word 0
 RVTEST_DATA_END