From: Mike Frysinger Date: Sat, 29 May 2021 16:46:06 +0000 (-0400) Subject: sim: frv: fix up a bunch of prototype warnings X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67514280fcbbbf872879b1a4a0aeb3453a24fb88;p=binutils-gdb.git sim: frv: fix up a bunch of prototype warnings Some were missing, some were unused, and some were partially renamed. --- diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index 348308d7b64..4ca57d3f4fd 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,19 @@ +2021-05-29 Mike Frysinger + + * cache.h (frv_cache_unlock): New prototype. + * frv-sim.h (frvbf_media_average): Likewise. + (frv_queue_data_access_exception_interrupt): Likewise. + (frv_queue_division_exception_interrupt): Likewise. + (frvbf_check_acc_range): Likewise. + (frvbf_check_swap_address): Likewise. + (frvbf_*_multiple_*): Rename prototypes to ... + (frvbf_*_quad_*): ... these. + * profile-fr500.c (use_is_cc_complex): Put #if 0 around. + * profile-fr550.c (use_is_ccr_complex): Likewise. + * profile.h (frv_ref_SI): New prototype. + * registers.h (frv_check_spr_read_access): Likewise. + (frv_check_spr_write_access): Likewise. + 2021-05-29 Mike Frysinger * cache.c (non_cache_access): Add parentheses. diff --git a/sim/frv/cache.h b/sim/frv/cache.h index 2b9eca8545b..866fe448948 100644 --- a/sim/frv/cache.h +++ b/sim/frv/cache.h @@ -234,6 +234,8 @@ frv_cache_write (FRV_CACHE *, SI, char *, unsigned); int frv_cache_preload (FRV_CACHE *, SI, USI, int); int +frv_cache_unlock (FRV_CACHE *, SI); +int frv_cache_invalidate (FRV_CACHE *, SI, int); int frv_cache_invalidate_all (FRV_CACHE *, int); diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h index 317bfd8dcd5..d00ff6aff6d 100644 --- a/sim/frv/frv-sim.h +++ b/sim/frv/frv-sim.h @@ -641,6 +641,7 @@ void frvbf_media_register_not_aligned (SIM_CPU *); void frvbf_media_acc_not_aligned (SIM_CPU *); void frvbf_media_cr_not_aligned (SIM_CPU *); void frvbf_media_overflow (SIM_CPU *, int); +SI frvbf_media_average (SIM_CPU *, SI, SI); /* Functions for queuing and processing interrupts. */ struct frv_interrupt_queue_element * @@ -679,6 +680,9 @@ frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI); struct frv_interrupt_queue_element * frv_queue_data_access_error_interrupt (SIM_CPU *, USI); +struct frv_interrupt_queue_element * +frv_queue_data_access_exception_interrupt (SIM_CPU *); + struct frv_interrupt_queue_element * frv_queue_instruction_access_error_interrupt (SIM_CPU *); @@ -690,6 +694,9 @@ frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *); enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int); +struct frv_interrupt_queue_element * +frv_queue_division_exception_interrupt (SIM_CPU *, enum frv_dtt); + struct frv_interrupt_queue_element * frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind); @@ -845,6 +852,8 @@ USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field); BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI); void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int); +SI frvbf_check_acc_range (SIM_CPU *, SI); +void frvbf_check_swap_address (SIM_CPU *, SI); void frvbf_clear_ne_flags (SIM_CPU *, SI, BI); void frvbf_commit (SIM_CPU *, SI, BI); @@ -864,12 +873,12 @@ extern int insns_in_slot[]; #define INSNS_IN_SLOT(slot) (insns_in_slot[slot]) /* Multiple loads and stores. */ -void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); -void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); -void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); -void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); -void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); -void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_load_quad_GR (SIM_CPU *, PCADDR, SI, SI); +void frvbf_load_quad_FRint (SIM_CPU *, PCADDR, SI, SI); +void frvbf_load_quad_CPR (SIM_CPU *, PCADDR, SI, SI); +void frvbf_store_quad_GR (SIM_CPU *, PCADDR, SI, SI); +void frvbf_store_quad_FRint (SIM_CPU *, PCADDR, SI, SI); +void frvbf_store_quad_CPR (SIM_CPU *, PCADDR, SI, SI); /* Memory and cache support. */ QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI); diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c index 41ee067c97a..f89e451bad8 100644 --- a/sim/frv/profile-fr500.c +++ b/sim/frv/profile-fr500.c @@ -126,12 +126,14 @@ set_use_not_cc_complex (SIM_CPU *cpu, INT cc) d->cur_cc_complex &= ~(((DI)1) << (cc)); } +#if 0 static int use_is_cc_complex (SIM_CPU *cpu, INT cc) { MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); return d->prev_cc_complex & (((DI)1) << (cc)); } +#endif void fr500_reset_fr_flags (SIM_CPU *cpu, INT fr) diff --git a/sim/frv/profile-fr550.c b/sim/frv/profile-fr550.c index af42d37a171..2bf1729135a 100644 --- a/sim/frv/profile-fr550.c +++ b/sim/frv/profile-fr550.c @@ -152,12 +152,14 @@ set_use_not_ccr_complex (SIM_CPU *cpu, INT ccr) d->cur_ccr_complex &= ~(((SI)1) << (ccr)); } +#if 0 static int use_is_ccr_complex (SIM_CPU *cpu, INT ccr) { MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); return d->prev_ccr_complex & (((SI)1) << (ccr)); } +#endif static void set_use_is_acc_mmac (SIM_CPU *cpu, INT acc) diff --git a/sim/frv/profile.h b/sim/frv/profile.h index cae20c4b580..9154a65630e 100644 --- a/sim/frv/profile.h +++ b/sim/frv/profile.h @@ -225,4 +225,6 @@ frv_model_trace_wait_cycles (SIM_CPU *, int, const char *); #define REGTYPE_FR 1 #define REGTYPE_ACC 2 +SI frv_ref_SI (SI); + #endif /* PROFILE_H */ diff --git a/sim/frv/registers.h b/sim/frv/registers.h index af2c293b724..4e5bde098bf 100644 --- a/sim/frv/registers.h +++ b/sim/frv/registers.h @@ -48,6 +48,8 @@ void frv_initialize_spr (SIM_CPU *); void frv_reset_spr (SIM_CPU *); void frv_check_spr_access (SIM_CPU *, UINT); +void frv_check_spr_read_access (SIM_CPU *, UINT); +void frv_check_spr_write_access (SIM_CPU *, UINT); void frv_fr_registers_available (SIM_CPU *, int *, int *); void frv_gr_registers_available (SIM_CPU *, int *, int *);