From: Clifford Wolf Date: Tue, 19 Jun 2018 12:29:38 +0000 (+0200) Subject: Be slightly less aggressive in "deminout" pass X-Git-Tag: yosys-0.8~70 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=675a44b41a2df2c02ceccda2434bc3efac3e5e2f;p=yosys.git Be slightly less aggressive in "deminout" pass Signed-off-by: Clifford Wolf --- diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index ed4e45762..0b8fd5246 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -57,7 +57,7 @@ struct DeminoutPass : public Pass { for (auto module : design->selected_modules()) { SigMap sigmap(module); - pool bits_written, bits_used, bits_inout; + pool bits_written, bits_used, bits_inout, bits_tribuf; dict bits_numports; for (auto wire : module->wires()) @@ -82,6 +82,25 @@ struct DeminoutPass : public Pass { if (cellport_in) for (auto bit : sigmap(conn.second)) bits_used.insert(bit); + + if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_")) + { + bool tribuf = (cell->type == "$_TBUF_"); + + if (!tribuf) { + for (auto &c : cell->connections()) { + if (!c.first.in("\\A", "\\B")) + continue; + for (auto b : sigmap(c.second)) + if (b == State::Sz) + tribuf = true; + } + } + + if (tribuf) + for (auto bit : sigmap(conn.second)) + bits_tribuf.insert(bit); + } } for (auto wire : module->selected_wires()) @@ -95,10 +114,15 @@ struct DeminoutPass : public Pass { if (bits_numports[bit] > 1 || bits_inout.count(bit)) new_input = true, new_output = true; - if (bits_written.count(bit)) + if (bits_written.count(bit)) { new_output = true; - else if (bits_used.count(bit)) - new_input = true; + if (bits_tribuf.count(bit)) + goto tribuf_bit; + } else { + tribuf_bit: + if (bits_used.count(bit)) + new_input = true; + } } if (new_input != new_output) {