From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 09:03:56 +0000 (+0200)
Subject: Added RTLIL::Module::wire(id) and cell(id) lookup functions
X-Git-Tag: yosys-0.4~398
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=675cb93da9e67f5c2fe8a3760de5893176ea906d;p=yosys.git

Added RTLIL::Module::wire(id) and cell(id) lookup functions
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5709875ec..db85f9e3d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -274,6 +274,16 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me
 	return selection_stack.back().selected_member(mod_name, memb_name);
 }
 
+bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
+{
+	return selected_module(mod->name);
+}
+
+bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
+{
+	return selected_whole_module(mod->name);
+}
+
 RTLIL::Module::Module()
 {
 	refcount_wires_ = 0;
@@ -1502,6 +1512,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
 
 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
 {
+	log_assert(wire != nullptr);
 	this->wire = wire;
 	this->width = wire->width;
 	this->offset = 0;
@@ -1509,6 +1520,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
 
 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
 {
+	log_assert(wire != nullptr);
 	this->wire = wire;
 	this->width = width;
 	this->offset = offset;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6eb52cf2d..7c69ff64c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -358,6 +358,9 @@ struct RTLIL::Design
 	bool selected_whole_module(RTLIL::IdString mod_name) const;
 	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 
+	bool selected_module(RTLIL::Module *mod) const;
+	bool selected_whole_module(RTLIL::Module *mod) const;
+
 	bool full_selection() const {
 		return selection_stack.back().full_selection;
 	}
@@ -425,6 +428,9 @@ public:
 	void cloneInto(RTLIL::Module *new_mod) const;
 	virtual RTLIL::Module *clone() const;
 
+	RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
+	RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
+
 	RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
 	RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
 
@@ -663,8 +669,8 @@ struct RTLIL::SigBit
 
 	SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
 	SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
-	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(!wire || wire->width == 1); }
-	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { }
+	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); }
+	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); }
 	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); }
 	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
 	SigBit(const RTLIL::SigSpec &sig);