From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Dec 2022 13:18:21 +0000 (+0000)
Subject: add unit test for Mem class, need to add misaligned ld/st
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=676b8f55887e8e04f34ee00b065098b29c8f25bb;p=openpower-isa.git

add unit test for Mem class, need to add misaligned ld/st
---

diff --git a/src/openpower/decoder/isa/test_mem.py b/src/openpower/decoder/isa/test_mem.py
new file mode 100644
index 00000000..4436d07f
--- /dev/null
+++ b/src/openpower/decoder/isa/test_mem.py
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Funded by NLnet http://nlnet.nl
+
+import unittest
+from openpower.decoder.isa.mem import Mem
+from openpower.util import log
+
+
+class TestMem(unittest.TestCase):
+
+    def test_mem_align_ld(self):
+        m = Mem(row_bytes=8, initial_mem={})
+        m.st(4, 0x12345678, width=4, swap=False)
+        d = m.dump()
+        log ("dict", d)
+        self.assertEqual(d, [(0, 0x1234567800000000)])
+
+
+if __name__ == '__main__':
+    unittest.main()